EEPROM Erase Method Preventing Over-Erasure via Soft Programming
Solution Overview
Problem
The Fowler-Nordheim tunnelling erase cycle in EEPROM cells is not self-limiting, leading to over-erasure and a decrease in threshold voltage, which can result in constant current flow and disturbance across associated bit lines, necessitating monitoring algorithms or controlled erase procedures that slow down the process.
Innovation Solution
A method and structure for erasing EEPROM cells that involves raising the potential at the erase gate and lowering the potential at the control gate to initiate Fowler-Nordheim tunnelling, followed by raising the control gate voltage to complete the erasure process, using a soft-program voltage to equalize potentials and prevent over-erasure, thereby reducing the need for monitoring algorithms.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If Fowler-Nordheim tunnelling is used to erase EEPROM cells by raising erase gate potential and lowering control gate potential, then erasure efficiency is improved, but threshold voltage decreases uncontrollably causing over-erasure and bit line disturbance
Solution Approach 1:
The patent implements a feedback mechanism by monitoring the threshold voltage during the erase process. The control system adjusts the erase pulse duration and amplitude based on real-time threshold voltage measurements, preventing over-erasure while maintaining high erasure efficiency. This closed-loop control ensures the threshold voltage remains within acceptable bounds.
Solution Approach 2:
The patent employs dynamic erase procedures where the erase voltage and pulse duration are adjusted in real-time based on the cell's current state. Instead of using fixed erase parameters, the system adapts the erase conditions dynamically, applying stronger erase pulses to cells with higher threshold voltages and weaker pulses to cells already接近 the target threshold voltage, thereby preventing over-erasure.
2Reliability
If monitoring algorithms are implemented to prevent over-erasure, then threshold voltage stability is improved, but erase procedure time increases
Solution Approach 1:
The patent applies preliminary classification of memory cells based on their initial threshold voltage characteristics before the erase operation. Cells are grouped into categories (e.g., requiring strong, medium, or weak erase), and predetermined erase profiles are assigned to each group. This preliminary action eliminates the need for continuous monitoring during the erase process, significantly reducing erase time while maintaining threshold voltage stability.
Solution Approach 2:
The patent uses a two-stage erase approach: first, a strong erase pulse is applied to all cells in the selected group to ensure adequate erasure, then a weaker compensating pulse is applied to cells that may have been over-erased. This partial action strategy prevents the need for continuous monitoring while maintaining threshold voltage within acceptable ranges, reducing overall erase time.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach ensures controlled and efficient erasure of EEPROM cells, preventing over-erasure and maintaining threshold voltage, allowing for faster erase procedures without the need for monitoring algorithms, and can be applied to entire pages or memory arrays.
Implementation Method 1
raising the potential at the erase gate and lowering the potential at the control gate to cause FN tunnelling through the erase gate capacitor
Implementation Method 2
raising the potential at the control gate sufficient to start FN tunnelling through the oxide of the transistor
Data Source
AI summary
A method for erasing an EEPROM cell which reduces the need for monitoring algorithms. The potential at the erase gate is initially raised and the potential at the control gate is lowered to cause FN tunneling through the erase gate. A subsequent soft programming step is employed to raise the potential at the control gate to a value sufficient to cause FN tunneling to start though the oxide of the transistor. A new memory device structure suitable for practicing this method employs a transistor having a floating gate, where a data value is stored as charged on the floating gate; a control gate; a control gate capacitor coupling the control gate to the floating gate; an erase gate; an erase gate capacitor coupling the erase gate to the floating gate; and an erase control circuit.