EEPROM Memory Cell Feeder Region Design for Fast Erase
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Solution Overview
Problem
EEPROM memory cells with coupler regions face challenges in achieving a large and time-independent coupling ratio between the coupler region and the floating gate, leading to slow erase times and high erase voltages due to the slow formation of the inversion layer in P-type coupler regions, resulting in poor linearity of the erase threshold voltage.
Innovation Solution
The EEPROM memory cell design includes a semiconductor body with a first and second well, a drain and source, a second channel region, and at least one feeder region of opposite conductivity type, forming an uninterrupted conducting path with the floating gate, which provides majority carriers for fast inversion during an erase operation, thereby reducing the depletion layer width and increasing the coupling ratio.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a P-type coupler region is used in the EEPROM memory cell, then the structure is simple and widely used in analog and mixed signal applications, but the inversion layer formation is slow causing a wide depletion layer which results in a small coupling ratio
Solution Approach 1:
The patent applies local quality by creating an N-type feeder region specifically within the P-type coupler region to provide localized majority carriers (holes) for fast inversion layer formation at the coupler-channel interface, while maintaining the overall P-type coupler region structure for simplicity. This localized doping modification resolves the contradiction by improving coupling ratio without requiring complete structural redesign.
Solution Approach 2:
The patent changes the doping parameter by introducing an N-type feeder region with opposite conductivity type to the P-type coupler region. This parameter change (adding opposite polarity doping) provides abundant holes for rapid inversion layer formation, thereby increasing the coupling ratio while maintaining the P-type coupler region's structural simplicity.
2Ease of manufacture
If a P-type coupler region is used in the EEPROM memory cell, then the structure is simple, but the time to erase the EEPROM memory cell is long
Solution Approach 1:
The N-type feeder region provides localized majority carriers (holes) specifically where needed for fast inversion layer formation during erase operations. This localized quality enhancement accelerates the erase process by enabling rapid carrier supply to the coupler-channel interface, reducing erase time while preserving the overall simple P-type coupler region structure.
Solution Approach 2:
The N-type feeder region is pre-formed during fabrication to stockpile majority carriers (holes) in advance. During erase operations, these pre-positioned carriers are immediately available to form the inversion layer rapidly, eliminating the time delay associated with slow carrier generation in conventional P-type coupler regions.
3Ease of manufacture
If a P-type coupler region is used in the EEPROM memory cell, then the structure is simple, but the absolute value of the erase voltage is large
Solution Approach 1:
The N-type feeder region creates a localized high-carrier-density zone that enhances the coupling efficiency. This improved coupling ratio means that a smaller erase voltage is sufficient to achieve the desired floating gate voltage, thereby reducing the power requirement while maintaining the simple P-type coupler region overall structure.
Solution Approach 2:
By changing the doping parameter and introducing the N-type feeder region, the patent achieves a larger coupling ratio that reduces the magnitude of erase voltage needed. The opposite polarity doping creates favorable electric field conditions that lower the voltage threshold for effective erase operations.
4Ease of manufacture
If a P-type coupler region is used in the EEPROM memory cell, then the structure is simple, but the EEPROM memory cell may have a bad linearity of the final erase threshold voltage to the erase voltage for a short erase time
Solution Approach 1:
The N-type feeder region creates a controlled local environment with abundant majority carriers that ensures consistent and predictable inversion layer formation. This localized carrier supply mechanism improves the linearity between erase voltage and erase threshold voltage by eliminating the variability and delays associated with slow carrier generation in conventional P-type coupler regions.
Solution Approach 2:
The pre-formed N-type feeder region stocks majority carriers in advance, ensuring that the inversion layer formation process is consistent and predictable. This preliminary preparation of carriers leads to better linearity in the erase characteristics, as the carrier supply is no longer limited by slow generation processes that cause variability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design reduces the absolute value of the erase voltage required and shortens erase time, while improving the linearity of the erase threshold voltage, simplifying the design and enhancing manufacturability by avoiding under-erase and over-erase situations.
Implementation Method 1
The at least one feeder region provides majority carriers of the second well to the second channel region so that a portion of the second channel region adjoining the top surface of the semiconductor body is inverted during an erase operation
Implementation Method 2
During an erase operation, an erase voltage is applied in the coupler region and is then capacitively coupled to the floating gate with a coupling ratio
Data Source
AI summary
An EEPROM memory cell with a coupler region is disclosed. The coupler region has a well and at least one feeder region formed in the well. The at least one feeder region is configured to provide majority carriers to a channel region defined in the well so that a portion of the channel region adjoining the top surface of the coupler region is inverted during an erase operation.