EEPROM Peripheral Area Reduction via Shared Filter Oscillator
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Solution Overview
Problem
Integrated circuits for EEPROM memories face challenges in reducing overall dimensions due to constraints on the peripheral portion, particularly high voltage elements and analogue components, which hinder the improvement of memory plane efficiency parameters despite shrinking the memory plane.
Innovation Solution
A method is introduced where a filter circuit from the communication interface is connected with an oscillator circuit to generate a stable clock signal for the write cycle, allowing for the use of a single oscillator circuit and dynamic frequency adjustment to improve accuracy and stability, thereby reducing the overall dimensions of the peripheral portion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If the memory plane is shrunk to improve efficiency parameter AE, then the ratio of memory plane area to total area increases, but the overall dimensions of the integrated circuit are not significantly reduced due to the fixed size of the peripheral portion
Solution Approach 1:
The filter circuit from the communication interface is repurposed to regulate the oscillation signal and generate the clock signal for write operations. This multi-functional use of the filter circuit reduces the need for dedicated components in the peripheral portion, allowing for size reduction while maintaining functionality.
Solution Approach 2:
The oscillation signal generation and clock signal generation functions are merged into a single oscillator circuit, with the filter circuit serving both the communication interface and the clock generation. This consolidation reduces the overall number of components and their total area in the peripheral portion.
2Measurement precision
If a dedicated stable signal generator is used for clock signal generation, then timing accuracy for write operations is improved, but the peripheral portion area increases
Solution Approach 1:
The filter circuit, originally designed for the communication interface, is utilized to regulate the oscillation signal and provide the necessary timing accuracy for write operations. This eliminates the need for a separate dedicated stable signal generator, reducing peripheral area while maintaining timing precision.
Solution Approach 2:
The filter circuit serves dual purposes: its original function in the communication interface and the additional function of regulating the oscillation signal for clock generation. This self-service approach reduces the need for external dedicated components.
3Reliability
If high voltage elements and analogue components are sized to meet stability and matching constraints, then reliability is improved, but the peripheral portion dimensions cannot be reduced
Solution Approach 1:
The filter circuit is reused for clock signal regulation, reducing the need for additional high voltage elements and analogue components. This multi-functional approach maintains reliability through proven circuit designs while minimizing the peripheral portion area.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the generation of stable clock signals for accurate write operations while reducing the peripheral portion's size, enhancing the memory plane's efficiency parameter and accommodating manufacturing and environmental variations.
Implementation Method 1
operatively connecting a filter circuit belonging to a communication interface physically connected to a bus, with an oscillator circuit and generating via the oscillator circuit an oscillation signal and regulating the oscillation signal with the filter circuit, so as to generate a clock signal for timing the write cycle
Data Source
AI summary
A method for writing to electrically erasable and programmable non-volatile memory and a corresponding integrated circuit are disclosed. In an embodiment a method includes operatively connecting a filter circuit belonging to a communication interface to an oscillator circuit, wherein the communication interface is physically connected to a bus, generating, by the oscillator circuit, an oscillation signal and regulating the oscillation signal by the filter circuit so as to generate a clock signal for timing a write cycle.