EEPROM Float Gate Width Optimization for Selective Erase
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Solution Overview
Problem
Existing EEPROM devices have limited erasing performance due to fixed coupling ratios between float and control gates, requiring all float gates to be erased simultaneously, which reduces efficiency and stability during erase operations.
Innovation Solution
The method involves forming float gate polycrystalline silicon layers with wider widths than the active regions, allowing for separate erasure of each float gate by adjusting the coupling ratio with control gates, and using bit line doping regions connected to different bit lines for precise voltage application during erase operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the width of float gate is made larger to increase coupling ratio, then erasing performance is improved, but device area increases
Solution Approach 1:
The patent divides the semiconductor substrate into multiple isolated active regions using isolation structures. Each active region contains its own float gate and control gate, allowing independent erasure operations. This segmentation enables selective erasure of individual float gates without affecting others, resolving the contradiction between improving erasing performance and controlling device area.
Solution Approach 2:
The patent implements different widths for float gates corresponding to different active regions. Specifically, float gates over first active regions have a first width, while float gates over second active regions have a second width that is different from the first width. This local variation in dimensions allows optimization of coupling ratios for specific erasure operations while maintaining compact overall device structure.
2Ease of operation
If all float gates are erased simultaneously to simplify control, then control complexity is reduced, but erasing efficiency decreases due to inability to perform selective erasure
Solution Approach 1:
The patent segments the memory device into multiple independently controllable units by isolating active regions with isolation structures. Each unit has its own float gate and control gate, enabling selective activation and erasure of individual units. This segmentation allows efficient selective erasure operations while maintaining relatively simple control logic, as each unit can be controlled independently through its control gate.
Solution Approach 2:
The patent enables dynamic control of erasure operations by allowing different voltage conditions to be applied to different control gates at different times. The isolation structures ensure that voltage applied to one control gate does not affect other float gates, providing dynamic flexibility in erasure sequencing and enabling efficient selective erasure without complex control mechanisms.
3Reliability
If coupling ratio between float gate and control gate is increased to improve erasure stability, then erase operation stability is improved, but power consumption increases
Solution Approach 1:
The patent optimizes coupling ratios locally for different active regions by varying float gate widths. Float gates over first active regions have a first width, while float gates over second active regions have a second width. This allows each region to have an optimized coupling ratio suited to its specific erasure requirements, achieving stable erasure operations while minimizing overall power consumption by not uniformly increasing all gate dimensions.
Solution Approach 2:
The patent applies erasure voltages selectively to only those control gates that require erasure at any given time, rather than applying voltage to all control gates simultaneously. The isolation structures ensure that the voltage applied to a specific control gate is confined to its corresponding float gate, enabling partial action that reduces unnecessary power consumption while maintaining erasure stability for the targeted gates.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the stability and efficiency of erase operations by increasing the coupling ratio between float and control gates, reducing power consumption, and enabling selective erasure of individual float gates, thereby improving overall performance.
Implementation Method 1
a tunneling oxide layer 206 disposed between the word line 201 and a first sidewall formed by the float gates 203 and the control gates 205
Implementation Method 2
a coupling ratio of the float gate to the control gate is limited
Data Source
AI summary
An EEPROM device, a forming method thereof, and a method for implementing an erase operation to the device are provided. The EEPROM device includes: a semiconductor substrate having active regions therein; a word line disposed on a first active region; float gate dielectric layers disposed on second active regions; float gates disposed on the float gate dielectric layers, wherein each of the float gates has a width larger than that of the second active region; control gates disposed on control gate dielectric layers which are disposed on the float gates; an isolation oxide layer disposed between the word line and the float gates along with the control gates; and bit line doping regions disposed on third active regions. Accordingly, an erase operation can be implemented from a bit line, and coupling ratios of a float gate to a control gate and to a bit line doping region can be improved.