EEPROM Floating Addressing Across Row Boundaries
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Solution Overview
Problem
Existing electrically programmable memory technologies face inflexibility in data organization and utilization due to the constraint of not being able to systematically position data in increasing order of addresses, leading to inefficient programming cycles that often exceed the end of a row, complicating data management.
Innovation Solution
A method for electrically programming non-volatile memory that addresses memory cells from an initial row and automatically switches to the next row when the end is reached, using global and local word lines to increment addresses and link programming voltages, allowing data to be stored in consecutive and increasing addresses across two rows.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If programming cycles are constrained to not exceed the end of a row, then data organization is simplified, but programming flexibility and efficiency deteriorate
Solution Approach 1:
The patent implements dynamic row switching during programming cycles. The system automatically transitions from the first row to the second row when the end of the first row is reached, allowing programming operations to continue seamlessly across row boundaries. This dynamic behavior resolves the contradiction by enabling flexible programming (improving productivity) while maintaining systematic address management (keeping complexity manageable).
Solution Approach 2:
The patent extends the programming space from a single-row constraint to a multi-row dimension. By introducing automatic row switching capability, the system allows programming cycles to span across multiple rows while maintaining consecutive address incrementation. This dimensional extension resolves the contradiction by providing both flexibility (programming can exceed row boundaries) and organization (addresses remain systematic).
2Adaptability or versatility
If data are written starting from an intermediate column, then programming flexibility improves, but address management complexity increases
Solution Approach 1:
The patent implements automatic address management through the programming system itself. When programming starts from an intermediate column or when row boundaries are reached, the system automatically increments addresses and switches rows without external intervention. This self-service mechanism resolves the contradiction by providing programming flexibility (can start anywhere) while eliminating address management complexity (automatic handling).
Solution Approach 2:
The patent employs feedback mechanisms where the programming system continuously monitors the current address position and automatically triggers row switching when the end of the first row is reached. This feedback loop ensures that addresses are systematically managed even when programming starts from intermediate columns, resolving the contradiction between flexibility and complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables flexible and efficient programming cycles that automatically manage address increments, ensuring all data are written on successive addresses without exceeding row boundaries, improving data organization and utilization in electrically programmable memories.
Implementation Method 1
These operations of erasing or programming a memory cell, and more particularly, the floating gate transistor FGT of the cell, are done for example, by a tunnel effect (Fowler Nordheim effect).
Data Source
AI summary
A method for electrically programming a non-volatile memory in which a programming cycle includes prior addressing of memory cells from an initial address corresponding to a first row and a column of a memory plane. The method may include addressing the memory cells in a second consecutive row when the end of the first row is reached to store data on bits with consecutive and increasing addresses in two consecutive rows.