EEPROM Floating Gate Architecture for Over-Erase Reduction
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Solution Overview
Problem
Conventional flash EEPROM cells face challenges in achieving smaller cell sizes due to over-erase issues in stack-gate structures and increased complexity and size in split-gate structures, which affect the scalability and integration of nonvolatile memory devices.
Innovation Solution
A novel method for manufacturing EEPROM cells involves forming a semiconductor substrate with a gate oxide layer, tunnel oxide layer, and polysilicon structures, including angle doping with specific dopant ions to create a floating gate and selective gate configuration that reduces transistor size and eliminates over-erase problems while maintaining the advantages of split-gate structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a stack gate structure is used, then the manufacturing process is simpler, but the chip size increases and over-erase problems occur
Solution Approach 1:
The gate structure is segmented into multiple gates (first control gate, second control gate, and select gate) positioned at different locations. This segmentation allows each gate to perform specific functions independently, reducing the overall area required while maintaining manufacturing simplicity.
Solution Approach 2:
The patent transitions from a planar gate arrangement to a three-dimensional configuration where gates are positioned at different heights and locations. The first and second control gates are arranged vertically, while the select gate is positioned laterally, utilizing spatial dimensions to reduce footprint.
2Reliability
If a split gate structure is used, then over-erase problems are eliminated, but the chip size increases and device complexity increases
Solution Approach 1:
The patent extracts the select gate function from the traditional split-gate configuration and positions it separately at a lateral location. This separation allows the control gates to be closely positioned vertically, reducing area while maintaining the over-erase protection function of the select gate.
Solution Approach 2:
The first control gate serves multiple functions: it controls the floating gate for data storage and works with the second control gate to prevent over-erase conditions. This multi-functionality reduces the need for additional structures, thereby reducing chip size.
3Reliability
If a split gate structure is used, then over-erase problems are eliminated, but device complexity increases
Solution Approach 1:
The patent merges the control functions into a unified multi-gate structure where the first control gate, second control gate, and select gate work together as an integrated system. This combination simplifies the overall device architecture compared to traditional split-gate structures while maintaining over-erase protection.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the fabrication of smaller-sized EEPROM cells with improved scalability and reduced complexity, addressing the limitations of conventional techniques by providing a more efficient and compact nonvolatile memory device architecture.
Implementation Method 1
forming a gate oxide layer over the semiconductor substrate... depositing a first polysilicon layer over the tunnel oxide layer and over the gate oxide layer
Implementation Method 2
angle doping with a first dopant at a first dose and a first energy level the floating gate to obtain a first doped region and a second doped region in the substrate
Data Source
AI summary
A method for manufacturing an Electrically Erasable Programmable Read-Only Memory (EEPROM) device includes providing a substrate and forming a gate oxide over the substrate. Also, the method includes providing a mask overlying the gate oxide layer, the mask defining a tunnel opening. The method additionally includes performing selective etching over the mask to form a tunnel oxide layer. The method includes forming a floating gate over the tunnel oxide layer and a selective gate over the gate oxide layer. The method includes angle doping a region of the substrate using the floating gate as a mask to obtain a first doped region. The method further includes forming a dielectric layer over the floating gate and a control gate over the dielectric layer. The method additionally includes angle doping a second region of the substrate using the selective gate as a mask to obtain a second doped region, wherein the first and second doped regions partially overlap.