EEPROM Gate Control Circuit Segmentation for Oxide Protection
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Solution Overview
Problem
Existing EEPROM memory cell gate control signal generating circuits are complex and costly due to the need for additional MOS transistors to isolate the gate oxide layers from high-voltage outputs, which complicates the circuit design.
Innovation Solution
The proposed EEPROM memory cell gate control signal generating circuit uses a high-voltage row decoding circuit with PMOS and NMOS transistors connected in a way that eliminates the need for additional transistors to isolate the gate oxide layers, simplifying the circuit and reducing costs by routing the total wordline voltage through PMOS and NMOS paths separately to avoid voltage interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If additional MOS transistors are added to isolate the gate oxide layers from high-voltage outputs, then the gate oxide layers are protected from voltage interference, but the circuit complexity and cost increase
Solution Approach 1:
The high-voltage row decoding circuit is segmented into separate PMOS and NMOS transistor paths. Each path independently handles either positive or negative high-voltage outputs, preventing voltage interference with gate oxide layers without requiring additional isolation transistors. This segmentation allows direct connection of drains to gates while maintaining protection.
2Reliability
If additional MOS transistors are added to isolate the gate oxide layers, then voltage interference is prevented, but the manufacturing cost increases
Solution Approach 1:
The circuit is divided into separate PMOS and NMOS paths that naturally prevent voltage interference, eliminating the need for additional isolation transistors and reducing manufacturing cost.
Solution Approach 2:
The PMOS and NMOS transistors serve dual functions: they act as switching elements for high-voltage output generation and simultaneously provide isolation protection for gate oxide layers. This multi-functionality reduces the total transistor count and manufacturing complexity.
3Device complexity
If the drains of PMOS and NMOS transistors are connected directly to output high-voltage signals, then the circuit is simplified, but voltage interference damages the gate oxide layers
Solution Approach 1:
The high-voltage output paths are segmented into separate PMOS and NMOS circuits. Each segment is dedicated to a specific voltage polarity, preventing opposite-polarity voltage interference from reaching the gate oxide layers while maintaining circuit simplicity.
Solution Approach 2:
The separate PMOS and NMOS transistor paths act as intermediaries that control and isolate voltage signals. By routing positive and negative high-voltage signals through distinct transistor paths, the circuit prevents direct voltage interference while maintaining simple direct connections.
Data Source
AI summary
An EEPROM memory cell gate control signal generating circuit, which includes a high-voltage row decoding circuit and a plurality of word selection circuits; the output of the high-voltage row decoding circuit is divided into two routes, which output a first total wordline voltage used for providing the erasing positive voltage and a second total wordline voltage used for providing the erasing negative voltage, respectively; besides, the two-route voltages are inputted into the individual word selection circuits respectively, which avoids the influence of the erasing positive voltage on the grid oxide layer of an NMOS transistor and the influence of the erasing negative voltage on a PMOS transistor, and can save the MOS transistor used for isolating the grid oxide layer.