EEPROM Memory Architecture Isolation Barrier
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Solution Overview
Problem
EEPROMs face high energy consumption and bulk due to high voltages required for writing, which is inefficient and increases the load on the chip's substrate.
Innovation Solution
The implementation of an EEPROM with a semiconductor substrate featuring memory cells organized in a matrix with an isolation barrier, including a buried layer and a wall extending to the substrate surface, allowing for reduced voltages during writing by isolating memory cells and applying specific voltage configurations to achieve the Fowler-Nordheim effect.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high voltages (+/-15V) are applied to the state transistor during writing, then the Fowler-Nordheim effect can be achieved for charge injection, but energy consumption increases and bulk on the substrate increases
Solution Approach 1:
The substrate is segmented into isolated regions using isolation barriers comprising buried layers and vertical walls. This segmentation allows independent voltage control of each memory cell region, enabling the Fowler-Nordheim effect to be achieved locally with lower voltages rather than requiring high voltages across the entire substrate.
Solution Approach 2:
Isolation barriers act as intermediaries between adjacent memory cell regions. These barriers (comprising buried layers and vertical walls extending to the substrate surface) enable electrical isolation, allowing lower voltages to be applied while still achieving the necessary electric field strength for charge injection through the Fowler-Nordheim effect in targeted cells.
2Reliability
If high voltages (+/-15V) are applied to the state transistor during writing, then charge injection via Fowler-Nordheim effect is enabled, but bulk on the substrate increases
Solution Approach 1:
The substrate is divided into isolated regions by isolation barriers, allowing localized charge injection in specific memory cells without requiring high voltages across the entire substrate. This reduces the overall bulk and high voltage device requirements on the chip.
Solution Approach 2:
The isolation barriers create regions with different electrical characteristics. Within each isolated region, the electric field can be concentrated and controlled independently, enabling effective Fowler-Nordheim charge injection with lower voltages and reducing the need for extensive high voltage infrastructure on the substrate.
3Use of energy by moving object
If isolation barriers with buried layers and vertical walls are implemented, then voltage requirements for writing are reduced and energy consumption decreases, but device complexity and manufacturing complexity increase
Solution Approach 1:
The isolation barrier structure segments the substrate into independent regions using buried layers and vertical walls. This segmentation enables lower operating voltages and reduced energy consumption during write operations, as each region can be independently controlled without requiring high voltages across the entire array.
Solution Approach 2:
The isolation barriers extend in the vertical dimension from the buried layer to the substrate surface, creating three-dimensional isolation structures. This vertical dimension provides effective electrical isolation that enables lower voltage operation, offsetting the increased structural complexity with significant energy consumption reductions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution reduces the voltage requirements for writing, lowering energy consumption by approximately 30% and minimizing the burden on high voltage devices, thereby optimizing the EEPROM's performance.
Implementation Method 1
an isolation barrier comprising a buried layer, and at least one wall extending from the buried layer to the surface of the substrate and perpendicularly to the buried layer, the isolating barrier forming an interior substrate which surrounds at least one of the memory cells and isolates it from the remainder of the substrate
Implementation Method 2
The injections and extractions of charges take place via an injection window INJT here situated on the side of the source TEs of the state transistor TE, enabling the implementation of the Fowler-Nordheim effect
Data Source
AI summary
In an embodiment an electrically erasable programmable readable memory includes a plurality of memory cells organised in a memory plane arranged in a matrix fashion in rows and in columns, wherein each memory cell includes a state transistor having a source region, a drain region, an injection window situated on the side of the drain, a control gate and a floating gate and an isolation transistor having a source region, a drain region and a gate; and an isolation barrier including a buried layer and at least one wall extending from the buried layer to a surface of a substrate, wherein the at least one wall is perpendicular to the buried layer, and wherein the isolating barrier forms an interior substrate surrounding at least one of the memory cells and isolating it from the remainder of the substrate.