EEPROM Transistor Integration for LCD Driver Low Voltage Operation
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Solution Overview
Problem
Conventional EEPROM devices in mobile devices require high voltages for programming and erasing, which is incompatible with the low voltage driving systems used in liquid crystal display units, leading to challenges in reducing the size of non-volatile memory devices while maintaining storage capacity and preventing punchthrough between n-wells.
Innovation Solution
The EEPROM device is integrated with an access transistor and an erase transistor, where the EEPROM transistor is placed between the access and erase transistors, with a floating gate extending between them, allowing for low voltage operation and reducing the device area by spacing the n-wells apart to prevent electrical influence and punchthrough.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high voltage is applied to the body of the erase transistor to perform erasing, then erasing function is achieved, but punchthrough may occur in the access transistor due to electrical influence from the second n-well
Solution Approach 1:
A device isolating layer is introduced between the first n-well (containing access transistor) and the second n-well (containing erase transistor) to act as an electrical intermediary that blocks the harmful voltage influence while allowing the erase transistor to function. This isolating layer prevents punchthrough in the access transistor during erasing operations by blocking the electrical field from the high-voltage second n-well.
2Reliability
If the first and second n-wells are spaced apart by a predetermined distance to prevent electrical influence, then punchthrough is prevented, but the overall device area increases
Solution Approach 1:
The device isolating layer is positioned vertically between the first and second n-wells rather than requiring horizontal spacing. This dimensional transition from lateral separation to vertical isolation allows the n-wells to be placed closer together in the planar direction, reducing device area while maintaining electrical isolation to prevent punchthrough.
3Reliability
If conventional EEPROM device structure is used, then high voltage programming and erasing are achieved, but compatibility with low voltage LCD driving system is lost
Solution Approach 1:
The EEPROM device is segmented into functionally separate regions: the first n-well contains the access transistor and EEPROM transistor for data access operations at low voltage, while the second n-well contains the erase transistor for erasing operations at high voltage. The device isolating layer enables these segments to operate at different voltages independently, achieving both low-voltage compatibility for LCD driving and high-voltage capability for erasing.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables the EEPROM device to operate at low voltages, reducing the overall area of the non-volatile memory device and enhancing integration density without compromising storage capacity or increasing the risk of punchthrough.
Implementation Method 1
a device isolating layer extending adjacent a surface of the semiconductor substrate... to prevent an electrical influence upon the first n-well by the voltage applied to the second n-well
Data Source
AI summary
Non-volatile memory devices according to embodiments of the present invention include an EEPROM transistor in a first portion of a semiconductor substrate, an access transistor in a second portion of the semiconductor substrate and an erase transistor in a third portion of the semiconductor substrate. The second portion of the semiconductor substrate extends adjacent a first side of the first portion of the semiconductor substrate and the third portion of the semiconductor substrate extends adjacent a second side of the first portion of the semiconductor substrate. The first and second sides of the first portion of the semiconductor substrate may be opposite sides of the first portion of the semiconductor substrate. The access transistor has a first source/drain terminal electrically connected to a first source/drain terminal of the EEPROM transistor and the erase transistor has a first source/drain terminal electrically connected to a second source/drain terminal of the access transistor.