EEPROM Local Well Breakdown Voltage Management

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Solution Overview

Problem

EEPROM memories face challenges with high write voltages leading to breakdowns and leakages at transistor junctions, limiting the reliability and efficiency of programming and erasing operations, and existing solutions are not well-suited for small memory devices like RFID tags or autonomous memories.

Innovation Solution

A memory architecture with a local well at floating potential and dummy bit lines is used to increase the potential of the local well during programming, reducing the voltage across junctions and allowing higher voltages to be applied without reaching breakdown, while maintaining compactness and low power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If high voltage pulse (10-20V) is applied for programming/erasing EEPROM, then programming and erasing operations can be performed, but breakdowns and leakages occur at source/drain junctions

Engineering Contradiction:

Improveprogramming and erasing operationVSAvoidbreakdown and leakage at junctions

Core Design Contradiction:

ReliabilityVSObject-affected harmful factors

Solution Approach 1:

A local well at floating potential is introduced as an intermediary structure between the substrate and the memory cell junctions. This local well acts as a mediator that absorbs part of the voltage stress during high-voltage programming operations, preventing direct breakdown at the source/drain junctions while enabling the necessary high voltages to be applied for programming and erasing

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The potential of the local well is dynamically changed during programming operations. By increasing the potential of the local well simultaneously with the application of the programming pulse, the voltage distribution across the junctions is modified, reducing the electric field intensity at critical junctions and preventing breakdown while maintaining programming effectiveness

Inventive Principle:

Principle #35Parameter changes

2Reliability

If voltage Vp is increased to ensure correct erase and programming, then programming and erasing operations are reliable, but leakage currents increase significantly

Engineering Contradiction:

Improveerase and programming operationVSAvoidleakage current

Core Design Contradiction:

ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The local well at floating potential serves as an intermediary that redistributes the voltage stress during high-voltage operations. This mediator structure allows the system to operate at higher voltages necessary for reliable programming and erasing while the floating potential configuration minimizes avalanche breakdown and associated leakage currents at the junctions

Inventive Principle:

Principle #24Intermediary (Mediator)

3Reliability

If tunnel oxide thickness is reduced to increase coupling factor, then memory cell coupling improves, but maximum possibilities are reached with thickness less than 70 Å

Engineering Contradiction:

Improvecoupling factorVSAvoidtunnel oxide thickness limitation

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

Instead of continuing to reduce tunnel oxide thickness to improve coupling, the invention changes the voltage distribution parameter by introducing the local well at floating potential. This parameter change allows achieving the necessary coupling effect through voltage management rather than geometric scaling, avoiding the limitations and reliability issues associated with extremely thin oxides

Inventive Principle:

Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach prevents breakdowns and leakages, enables reliable high-voltage programming, and improves data retention with reduced coupling factor, leading to more resilient memory cells that can handle more erase/programming cycles.

Implementation Method 1

the programming circuitry is configured for increasing the potential of the local well by making a reverse current flow in the PN junction

Methodology Applied

Scientific EffectPN junction reverse current: Diode

Implementation Method 2

The programming or the erasing of a floating-gate transistor consists in the injection or the extraction of electrical charges into or from the gate of the transistor by tunnel effect (Fowler-Nordheim effect)

Methodology Applied

Scientific EffectFowler-Nordheim tunnel effect:

Implementation Method 3

when the voltage Vp comes close to the maximum voltages permitted for the components in question, large leakage currents appear, generally by the avalanche effect

Methodology Applied

Scientific EffectAvalanche effect: Avalanche Breakdown

Data Source

PatentUS9747053B1Apparatus and method for EEPROM select transistor breakdown voltage management

Publication Date: 2017.08.29 STMICROELECTRONICS (ROUSSET) SAS

AI summary

A memory device of the non-volatile electrically-erasable and programmable memory type is provided. The memory device includes a matrix memory plane of memory cells connected to bit lines. Programming circuitry is configured to select a memory cell and to apply a programming pulse to the corresponding bit line. The memory plane is disposed in a local well at a floating potential and the programming circuitry is configured to increase the potential of the local well simultaneously with the application of the programming pulse to the bit line of a selected memory cell.