EEPROM Cell With Low-Voltage Read and High-Voltage Erase/Write Paths
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing EEPROM memory cells operate at high voltages, requiring large junctions and thick gate oxides, which hinder scaling to smaller geometries and limit read current flow, making it difficult to reduce cell size while maintaining functionality.
Innovation Solution
The EEPROM cell design incorporates a separate high-voltage write/erase gate and low-voltage read gate, with a thinner spacer oxide under the read gate, allowing independent control of read and write/erase paths, and includes features like dummy cells and common source lines to facilitate scaling and improve contact formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high voltage is used for write/erase operations, then write and erase functionality is achieved, but read current flow is resisted due to thick gate oxide
Solution Approach 1:
The gate structure is segmented into two independent gates: a first gate (write/erase gate) with thick oxide for high-voltage write and erase operations, and a second gate (read gate) with thin oxide for low-voltage read operations. This segmentation allows each gate to be optimized for its specific function without compromise.
Solution Approach 2:
Different regions of the gate structure have different oxide thicknesses tailored to their specific functions. The first gate region has thick oxide (50-200 nm) for write/erase durability, while the second gate region has thin oxide (2-10 nm) for efficient read current flow.
2Reliability
If thick gate oxide is used to support high voltage write/erase operations, then write and erase reliability is improved, but cell size must be kept large to provide sufficient read current
Solution Approach 1:
The gate is divided into two independent gates with different oxide thicknesses, allowing the read gate to have thin oxide that enables sufficient read current in a smaller cell area, while the write/erase gate maintains thick oxide for reliability.
Solution Approach 2:
The thin oxide region under the read gate enables efficient read current flow in a compact area, while the thick oxide region under the write/erase gate provides the necessary voltage withstand capability for reliable operation.
3Reliability
If high voltage is used for all operations, then write and erase operations are performed, but read operations require large junctions and deep structures
Solution Approach 1:
The device is segmented into two independent gate systems: the first gate for high-voltage write/erase operations and the second gate for low-voltage read operations. This allows read operations to use simple shallow junctions while write/erase operations use the high-voltage first gate.
Solution Approach 2:
The second gate is designed with thin oxide specifically for read operations, enabling simple junction structures at low voltage, while the first gate maintains thick oxide for high-voltage write/erase operations on deeper junctions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design enables memory cells to operate at lower voltages, reducing transistor area by up to 50% and allowing finer geometry scaling, while maintaining high read current and reliability, eliminating the need for separate source lines, and improving contact formation.
Implementation Method 1
a floating gate oxide between the floating gate and the substrate, and a read gate oxide between the read gate and the substrate
Implementation Method 2
the read gate oxide is thinner than the floating gate oxide... the dimension of the cell into the page must be kept relatively large. Thus, the size of this memory cell cannot be easily scaled down to smaller geometries, while still providing sufficient read current
Data Source
Figure 1
Figure 2
Figure 3
AI summary
An electrically erasable programmable read only memory (EEPROM) cell may include a substrate including at least one active region, a floating gate adjacent the substrate, a write/erase gate defining a write/erase path for performing high voltage write and erase operations, and a read gate defining a read path for performing low voltage read operations, wherein the read path is distinct from the write/erase path. This allows for a smaller read gate oxide, thus allowing the cell size to be reduced. Further, the EEPROM cell may include two independently controllable read gates, thereby defining two independent transistors which allows better programming voltage isolation. This allows the memory array to be drawn using a common source instead of each column of EEPROM cells needing its own source line. This makes the array more scalable because the cell x-dimension would otherwise be limited by each column needing two metal 1 pitches.