EEPROM Array with Shared Capacitor and Symmetric Cell Layout
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Solution Overview
Problem
Current non-volatile memory technologies, such as EEPROM, occupy large areas due to the layout of memory cells and capacitors, leading to increased costs and inefficiencies.
Innovation Solution
The design incorporates a 2x2 sub-memory array layout with symmetric memory cells sharing common connection points, including bit lines, word lines, and common source lines, reducing the overall area and allowing for byte-writing and byte-erasing without additional isolating transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the traditional non-volatile memory cell layout with capacitor at one side of transistor is used, then the memory can store charges to change gate voltage, but the area occupied by each memory cell increases
Solution Approach 1:
The patent merges the storage function of four memory cells into a single shared capacitor. The capacitor is positioned at the intersection of four memory cells, allowing one capacitor to serve multiple cells through shared bit lines and word lines. This consolidation dramatically reduces the area required per memory cell while maintaining the non-volatile storage capability through electrical charging and discharging of the shared capacitor.
Solution Approach 2:
The patent transitions from a planar one-capacitor-per-cell layout to a three-dimensional shared architecture where a single capacitor serves multiple cells across different spatial dimensions. The capacitor is strategically positioned to interface with four different memory cells through orthogonal bit lines and word lines, effectively utilizing vertical and horizontal routing dimensions to reduce overall footprint.
2Ease of operation
If two bit lines are provided between adjacent byte-memory cells, then memory operations can be performed, but the area occupied increases
Solution Approach 1:
The patent implements multi-functional bit lines and word lines that serve multiple memory cells simultaneously. Each bit line and word line acts as a universal bus that can select and operate on any of the four memory cells connected to it. This universal addressing scheme enables complete memory operations (read, write, erase) on any cell using the same physical lines, eliminating the need for additional dedicated lines between cells.
3Device complexity
If capacitors are located at one side of transistors in memory cells, then the memory structure is simple, but the area occupied increases and cost rises
Solution Approach 1:
The patent merges the storage function of four memory cells into a single shared capacitor. The capacitor is positioned at the intersection of four memory cells, allowing one capacitor to serve multiple cells through shared bit lines and word lines. This consolidation dramatically reduces the area required per memory cell while maintaining the non-volatile storage capability through electrical charging and discharging of the shared capacitor.
Data Source
AI summary
An area saving electrically-erasable-programmable read-only memory (EEPROM) array, having: a plurality of parallel bit lines, a plurality of parallel word lines, and a plurality of parallel common source lines. The bit lines are classified into a plurality of bit line groups, containing a first group bit line and a second group bit line; the word line includes a first word line; and the common source lines include a first common source line. In addition, a plurality of sub-memory arrays are provided. Each sub-memory array contains a first, second, third, and fourth memory cells. Wherein, the first and second memory cells are symmetrically arranged, and the third and fourth memory cells are symmetrically arranged; also, the first and second memory cells, and the third and fourth memory cells are symmetrically arranged with the first common source line as a symmetric axis.