Scalable EEPROM Cell Pair With Shared Source Access Transistor
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Solution Overview
Problem
Conventional EEPROM systems face challenges in scaling to sub-0.35 micron processes due to large transistor sizes required for high programming voltages, leading to complex memory operations and fabrication processes that are costly and prone to yield management issues.
Innovation Solution
The EEPROM array design incorporates shared source access transistors and memory transistors, allowing for a 1.5 transistor per bit configuration, which reduces the need for high programming voltage across drain junctions and bit lines, enabling scaling to sub-0.35 micron processes with simplified fabrication and operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional EEPROM cells use separate access transistors and memory transistors with high programming voltage, then reliable erase and program operations can be achieved, but the transistor size becomes large and scaling to sub-0.35 micron processes becomes difficult
Solution Approach 1:
The patent merges the access transistor and memory transistor into a single integrated transistor structure. The gate dielectric layer serves dual purposes: as the gate dielectric for the access transistor when controlled by the select line, and as the tunneling dielectric for the memory transistor when subjected to programming voltage. This consolidation eliminates the need for separate transistors while maintaining the functional requirements for both access and memory operations, enabling scaling to sub-0.35 micron processes.
2Reliability
If high programming voltage is applied to drain junctions and bit lines for erase operations, then floating gate charge can be trapped effectively, but the fabrication process becomes complex and costly
Solution Approach 1:
The patent extracts the high voltage stress from the drain junctions and bit lines during erase operations and redirects it to be applied between the control gate and the floating gate through the gate dielectric layer. By applying programming voltage to the control gate while the select gate is at a lower potential, the electric field is concentrated across the gate dielectric to enable tunneling, rather than stressing the drain junctions. This eliminates the need for complex high voltage routing to drain lines while achieving effective erase operations.
3Reliability
If large transistor sizes are used to handle high programming voltages, then voltage control is reliable, but the memory array density and scalability are reduced
Solution Approach 1:
The patent changes the voltage application parameters and control strategy. Instead of applying high programming voltage to drain junctions requiring large transistor dimensions for voltage control, the invention applies the programming voltage between the control gate and floating gate through the gate dielectric. The select line can be held at a lower potential (e.g., 0V or negative voltage) during programming, allowing the same transistor structure to handle both low-voltage selection and high-voltage programming without requiring large dimensions, thereby enabling higher density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design allows for efficient scaling of EEPROM systems to smaller processes, simplifying the fabrication process and reducing costs while maintaining reliable memory operations, as evidenced by the ability to perform erase, program, and read operations without applying high programming voltage to drain junctions or bit lines.
Implementation Method 1
the floating gates of NVM transistors 121-122 are coupled to a fraction of the programming voltage VPP, which is enough to produce tunneling currents from the underlying diffusion extension region 235 through the thin gate dielectric region 233
Data Source
AI summary
A non-volatile memory including one or more EEPROM cell pairs. Each EEPROM cell pair includes three transistors and stores two data bits, effectively providing a 1.5 transistor EEPROM cell. An EEPROM cell pair includes a first non-volatile memory transistor, a second non-volatile memory transistor and a source access transistor. The source access transistor includes: a first source region continuous with a source region of the first non-volatile memory transistor; a second source region continuous with a source region of the second non-volatile memory transistor, and a third source region continuous with source regions of other non-volatile memory transistors located in the same row as the EEPROM cell pair.