EEPROM Single Gate Structure High Voltage Junction Breakdown
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Solution Overview
Problem
The fabrication of EEPROMs with a single gate structure in System on Chip (SOC) is complicated due to low junction breakdown voltage between source/drain regions and wells, limiting the application of high voltages required for programming and erasing operations.
Innovation Solution
The EEPROM design includes a floating gate access transistor with source and drain regions, and a control gate with impurity regions and well taps of higher impurity concentration, allowing for the application of high programming and erasing voltages without junction breakdown, using a CMOS fabrication process similar to logic devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single gate structure is used in EEPROM, then the fabrication process complexity is reduced and CMOS compatibility is improved, but the junction breakdown voltage between source/drain regions and wells becomes low, limiting high voltage application
Solution Approach 1:
The EEPROM device is divided into two separate regions: a first region containing the access transistor with source/drain regions, and a second region containing the control gate with impurity regions. This spatial segmentation allows independent optimization of each region's electrical characteristics, enabling the control gate region to have higher breakdown voltage while the access transistor maintains standard CMOS characteristics.
Solution Approach 2:
Different impurity concentrations are applied to different regions: the control gate region has higher impurity concentrations than the active area, creating locally enhanced breakdown voltage characteristics. The well taps are also designed with higher impurity concentrations than the surrounding wells, providing localized voltage stabilization without affecting the entire device structure.
2Ease of operation
If high voltage is applied to source/drain regions for programming and erasing operations, then data programming and erasing functionality is achieved, but junction breakdown occurs due to low breakdown voltage in standard CMOS wells
Solution Approach 1:
Well taps with higher impurity concentrations are formed in advance in the second region before the high voltage programming/erasing operations are performed. These pre-positioned well taps create localized high-breakdown regions that can withstand the high voltages required for Fowler-Nordheim tunneling, preventing junction breakdown before it occurs.
Solution Approach 2:
The well taps act as intermediary structures between the control gate impurity regions and the surrounding lower-doped wells. They provide a transition zone with intermediate electrical characteristics, allowing high voltage to be applied to the control gate for programming/erasing while the well taps absorb and distribute the voltage stress, preventing direct breakdown at the source/drain junctions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enables stable programming and erasing operations at high voltages, preventing junction breakdown and ensuring reliable operation of the EEPROM, simplifying the SOC fabrication process and allowing for the use of a typical CMOS process.
Implementation Method 1
In the programming operation mode and the erasing operation mode in which charges are trapped or released in a floating gate via a tunneling gate insulating layer
Data Source
AI summary
An electrically erasable programmable read-only memory (EEPROM) includes an access transistor having a floating gate and source/drain regions formed at opposite sides of the floating gate in a first well, a first well tap formed in the first well, a control gate located on a second region, first impurity regions formed at both sides of the control gate in the second region, and a second well tap formed in a third region. In order to erase information stored in a memory cell, a predetermined erasing voltage is applied to the source/drain regions of the access transistor and the first well tap, a ground voltage is applied to the first impurity regions in the second region, and a voltage, which is greater than 0V and less than a junction breakdown voltage between the active area and the first well, is applied to the second well tap.