Self-Aligned EEPROM Word Lines Defined by Spacer Sidewalls
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Solution Overview
Problem
Existing EEPROM cell technologies face non-uniformity issues in word line widths due to shifting during patterning, which affects the performance and reliability of memory devices.
Innovation Solution
The formation of self-aligned word lines between spacers in an EEPROM array, where spacers are used to sandwich and define the width of the word lines, ensuring consistent dimensions and avoiding the non-uniformity caused by shifting during the patterning process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional patterning methods are used to form word lines, then the manufacturing process is simple, but the word line width becomes non-uniform due to shifting
Solution Approach 1:
The patent applies preliminary action by forming spacers on the sidewalls of floating gates before forming the word lines. These spacers serve as pre-positioned alignment references that define the exact location and width of the word lines, preventing any shifting during subsequent patterning steps. The spacers are formed through depositing conformal layers and performing anisotropic etching, which establishes precise geometric boundaries before the word line material is deposited.
Solution Approach 2:
The patent uses spacers as intermediary structures that mediate between the floating gates and the word lines. These spacers act as alignment mediators, transferring the precise positioning information from the floating gate structure to the word line formation process. The spacers physically define the boundaries where word lines should be formed, ensuring uniform width without requiring complex alignment procedures.
2Reliability
If self-aligned word line formation is used, then word line width uniformity is improved, but the manufacturing process becomes more complex
Solution Approach 1:
The spacers are formed in advance as alignment references before word line deposition. This preliminary structuring establishes the exact geometry and position of future word lines, ensuring uniform width and improving device reliability. The preliminary spacer formation includes conformal layer deposition and anisotropic etching to create precise sidewall structures.
Solution Approach 2:
The spacers serve a dual function: they are structural components of the memory device and simultaneously serve as self-aligning references for word line formation. The self-service principle is applied because the spacers automatically provide the alignment information needed for word line positioning without requiring external alignment procedures, thereby improving reliability while maintaining manufacturing simplicity.
3Manufacturing precision
If multiple patterning steps are used to ensure word line precision, then manufacturing precision is improved, but productivity decreases
Solution Approach 1:
The spacers are formed as preliminary structures that pre-establish the alignment references for word lines. This preliminary action consolidates multiple alignment operations into a single spacer formation process, maintaining high positioning precision while reducing the total number of patterning steps required, thereby improving manufacturing throughput.
Solution Approach 2:
The patent merges the alignment reference function and the structural function into the single spacer component. By combining these functions, the patent eliminates the need for separate alignment marks and reference structures that would require additional patterning steps, thus maintaining precision while improving productivity through process integration.
Data Source
AI summary
An array of electrically erasable programmable read only memory (EEPROM) includes a first row of floating gate, a second row of floating gate, two spacers, a first row of word line and a second row of word line. The first row of floating gate and the second row of floating gate are disposed on a substrate along a first direction. The two spacers are disposed between and parallel to the first row of floating gate and the second row of floating gate. The first row of word line is sandwiched by one of the spacers and the adjacent first row of floating gate, and the second row of word line is sandwiched by the other one of the spacers and the adjacent second row of floating gate. The present invention also provides a method of forming said array of electrically erasable programmable read only memory (EEPROM).