EEPROM Memory Cell Spacer Fabrication for Reduced Standby Current
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Solution Overview
Problem
The scalability of EEPROM memory cells is limited by the minimum aperture size of the tunnel window, which restricts the reduction of memory cell size and increases standby current due to lithographic constraints.
Innovation Solution
The use of advanced spacer fabrication techniques allows for the creation of tunnel windows with feature sizes smaller than those achievable by conventional lithography, enabling reduced device geometries and narrower select gate widths, thereby minimizing standby current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional lithography is used to define the tunnel window, then the manufacturing process is simple and reliable, but the minimum aperture size is limited which increases memory cell size and standby current
Solution Approach 1:
The patent performs preliminary actions by forming spacers on the sidewalls of the tunnel window aperture before the actual aperture definition step. These spacers are formed with a thickness that determines the final aperture size, allowing precise control of the minimum aperture dimension before lithography is applied. This preliminary spacer formation enables sub-lithographic aperture sizes to be achieved while maintaining manufacturing reliability.
Solution Approach 2:
The patent introduces spacers as an intermediary element between the lithography process and the final aperture definition. The spacers act as a mediating structure that translates lithographic patterns into precisely controlled aperture dimensions. This intermediary approach allows the aperture size to be determined by spacer thickness rather than direct lithographic resolution, thereby achieving smaller aperture sizes than conventional lithography would permit.
2Area of stationary object
If the memory cell size is reduced to increase array density, then more devices fit in a given area, but the standby current increases which compromises device reliability
Solution Approach 1:
The patent applies local quality by creating a recessed tunnel window structure with localized doping regions. The tunnel window is recessed into the substrate and surrounded by selectively doped regions, creating localized electrical properties that reduce standby current leakage. This local structural modification allows the memory cell to maintain small overall dimensions while achieving low standby current through localized quality enhancement at critical interfaces.
Solution Approach 2:
The patent converts the potential harm of small aperture sizes (which would increase leakage) into a benefit by using the recessed structure and selective doping to create beneficial electrical field confinement. The recessed tunnel window, when combined with appropriate doping, creates potential barriers that suppress leakage currents. Thus, the small aperture size that would normally increase standby current is instead made to reduce it through the converted harmful effect into beneficial field confinement.
3Length of moving object
If the tunnel window aperture size is minimized to reduce memory cell dimensions, then device scaling is improved, but the manufacturing precision requirements increase beyond conventional lithography limits
Solution Approach 1:
The patent transitions from two-dimensional lithographic patterning to three-dimensional spacer-based definition. Instead of relying solely on planar lithographic resolution to define the aperture, the invention uses vertical spacer thickness (a third dimension) to control the aperture size. The spacers are formed conformally on sidewalls, and their thickness—controlled by deposition processes rather than lithography—determines the final aperture dimension, thereby achieving precision beyond conventional lithographic limits.
Solution Approach 2:
The patent changes the controlling parameter for aperture size from lithographic linewidth (two-dimensional parameter) to spacer thickness (one-dimensional parameter controlled by deposition). By shifting the critical dimension control to a different process parameter—spacer thickness formed by atomic layer deposition or chemical vapor deposition—the manufacturing precision is improved because thin film deposition can achieve sub-10nm thickness control, far exceeding lithographic resolution capabilities.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in significantly smaller memory cell sizes and lower standby currents, enhancing the scalability and efficiency of EEPROM memory cells while maintaining low power consumption.
Implementation Method 1
The spacer structure is formed over the aperture such that a distance between spacers on opposing sidewalls of the aperture is less than a limit of optical photolithography
Data Source
AI summary
A present invention is a method, and resulting device, for fabricating memory cells with an extremely small area and reduced standby current. The small area is accomplished by a judicious use of spacers which allows a tunnel window of a storage device to be fabricated in close proximity to an associated select gate and with a reduced gate width compared to typical devices. The tunnel window is recessed within an upper surface of a substrate. The tunnel window recess is made possible by selective etching of the substrate and oxides covering the substrate. A substantial reduction in the size of a tunnel window means device scaling is possible far beyond what is attainable with standard photolithography. Standby current is reduced significantly by fabricating a select device with complementary material types for the gate compared with the adjacent source/drain regions.