EEPROM Split Voltage Programming for Gate Oxide Reliability
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Solution Overview
Problem
High programming voltages in EEPROMs pose constraints on processing and reliability due to risks of transistor breakdown and premature aging, particularly in relation to punchthrough and leakage of source/drain junctions and gate oxide breakdown.
Innovation Solution
A method involving a split voltage approach where a positive voltage and a negative voltage are applied to the control gate and bit line respectively, with the difference between them being the programming voltage, reducing the voltage capacity constraints on transistors and enhancing reliability, while maintaining compatibility with conventional production processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a high programming voltage of 16 volts is used, then the programming function is achieved, but the reliability deteriorates due to risks of punchthrough, leakage of source/drain junctions and breakdown of gate oxides
Solution Approach 1:
The high programming voltage of 16V is segmented into two separate voltage applications: a positive voltage (e.g., 12V) applied to the control gate and a negative voltage (e.g., -4V) applied to the bit line. This segmentation allows the full programming voltage effect to be achieved through the voltage difference between the two terminals, while each individual voltage application remains within safe operating limits for the transistor structures, thereby preventing gate oxide breakdown and junction damage.
2Adaptability or versatility
If a split voltage approach with negative voltage is used, then the voltage capacity constraint is reduced, but the device complexity increases due to triple case technology and negative voltage switching requirements
Solution Approach 1:
Instead of applying the conventional approach where both control gate and bit line use positive voltages or ground, this invention inverts the voltage polarity on the bit line by applying a negative voltage during programming operations. This inversion enables the split voltage strategy to work with standard single-well NMOS technology, avoiding the need for complex triple-well structures or specialized negative voltage switching circuits, thereby reducing device complexity while maintaining voltage capacity adaptability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces the risk of gate oxide breakdown and maintains compatibility with conventional EEPROM production, avoiding complications and costs associated with negative voltage switching.
Implementation Method 1
Writing or erasing may be carried out on a floating-gate transistor by injecting electrical charges into the transistor gate, or removing them from it, by a tunnel effect (the Fowler-Nordheim effect), using a high programming voltage Vpp
Data Source
AI summary
An electrically programmable and erasable non-volatile memory point may have at least one floating-gate transistor connected to a bit line and to a ground line, and may be programmed with a programming voltage. In an erase phase of the memory point, a first, negative, voltage may be applied to the bit line and to the ground line. The absolute value of the first voltage may be smaller than a threshold value of a PN diode. A second positive voltage which is smaller than the programming voltage may be applied to the control gate of the floating-gate transistor. The difference between the second voltage and the first voltage may be equal to the programming voltage, and, in a writing phase, the first negative voltage may be applied to the control gate of the floating-gate transistor, and the second voltage may be applied to the bit line.