EEPROM Tunneling Transistor Gate Width Optimization
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Single gate structure EPROMs face challenges with unreliable electrical erasure, despite their simplified manufacturing process and compatibility with logic devices.
Innovation Solution
Incorporating a tunneling transistor with a narrower gate width and integrally joined source and drain junction regions, formed through ion implantation, to enable electrical erasure while maintaining a small cell size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a single gate structure is used in EPROM, then the manufacturing process is simplified and compatibility with logic devices is improved, but electrical erasure becomes unreliable
Solution Approach 1:
The invention divides the single gate structure into two separate gates: a first gate (control gate) and a second gate (tunneling gate). This segmentation allows the first gate to control program/erase operations while the second gate enables reliable electrical erasure through Fowler-Nordheim tunneling, resolving the contradiction between manufacturing simplicity and erasure reliability.
Solution Approach 2:
The dual gate structure provides multi-functionality where the first gate handles control and programming operations, while the second gate specifically enables electrical erasure. This universal design maintains compatibility with standard CMOS processes while adding the capability for reliable electrical erasure that single gate structures lack.
2Adaptability or versatility
If a stacked-gate structure is used in EPROM, then device integration is improved, but the manufacturing process becomes relatively complicated
Solution Approach 1:
The invention applies local quality by forming the second gate (tunneling gate) only in specific regions where erasure is needed, rather than using a full stacked-gate structure throughout. This selective application maintains the benefits of integration while avoiding the complexity of complete stacked-gate manufacturing.
Solution Approach 2:
Instead of vertically stacking gates in the third dimension (stacked-gate structure), the invention places the first and second gates side-by-side in the planar dimension. This dimensional change achieves the functional benefits of dual gates while maintaining a simpler manufacturing process compatible with standard CMOS technology.
3Loss of time
If the gate width of the tunneling transistor is reduced, then erase time is reduced and erasure reliability is improved, but the cell area increases
Solution Approach 1:
The invention makes the gate width a dynamic parameter, allowing it to be optimized for its specific function (erasure) rather than being constrained by the overall cell dimensions. The tunneling gate width can be independently adjusted to achieve fast erasure times while the overall cell area is managed through efficient layout of the dual gate structure.
Solution Approach 2:
The invention changes the critical parameter of gate width specifically for the tunneling transistor to optimize erasure performance. By independently controlling the second gate width (W2) to be narrower than the first gate width (W1), the patent achieves reduced erase time and improved erasure reliability without necessarily increasing the overall cell area, as the gates are arranged in a space-efficient dual-gate configuration.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables reliable electrical erasure of electrons trapped in the floating transistor, enhancing junction breakdown voltage and reducing erase time with adjustable erasure voltage, while maintaining a compact cell structure.
Implementation Method 1
a tunneling transistor formed on/over a semiconductor substrate and configured to erase electrons trapped in the floating transistor
Implementation Method 2
formed through ion implantation
Data Source
AI summary
An electrical erasable programmable read-only memory (EEPROM) including a floating transistor formed on a semiconductor substrate and a tunneling transistor formed on a semiconductor substrate and configured to erase electrons trapped in the floating transistor. The tunneling transistor has a source junction region and a drain junction region that are integrally joined by lateral diffusion. The EPROM maintains a small cell size without any additional mask process, and is useable as an MTP EEPROM because electrical erasure is enabled. In addition, the adjustment of the width of a gate constituting the tunneling transistor ensures an improved degree of freedom to adjust an erasure voltage can be enhanced.