EEPROM Unit Cell Block Cross-Coupled Transistors Reference Elimination
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Solution Overview
Problem
Conventional EEPROMs require a reference cell transistor for data read operations, leading to increased data access time and current consumption, especially as power voltage levels decrease, due to the need for differential amplification and comparison.
Innovation Solution
A semiconductor memory device utilizing cross-coupled MOS transistors in both the sensing unit and unit cell to sense and amplify voltage differences without a reference cell transistor, along with a sensing protecting unit to manage high voltage applications and an enabling unit for data transfer, allowing for high-speed data reading.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a reference cell transistor is used for data read operations, then data reading can be performed, but data access time increases
Solution Approach 1:
The patent removes the reference cell transistor from the memory cell structure. Instead of using a separate reference cell for comparison, the invention uses the bit line itself as the reference, eliminating the need for additional reference cell transistors and reducing the time required for data access operations.
Solution Approach 2:
The patent combines the reference function with the bit line structure. The bit line serves dual purposes: as the signal transmission line and as the reference for comparison. This merging eliminates separate reference cell components and reduces the overall access time by consolidating functions.
2Reliability
If a reference cell transistor is used for data read operations, then data reading can be performed, but current consumption increases
Solution Approach 1:
The patent extracts and removes the reference cell transistor from the circuit, eliminating the current consumption associated with operating a separate reference cell. The bit line itself is used for comparison, significantly reducing the current required for read operations.
Solution Approach 2:
The bit line serves itself by performing both signal transmission and reference comparison functions. This self-service approach eliminates the need for dedicated reference cell transistors that would consume additional current, allowing the system to achieve data reading with minimal power consumption.
3Use of energy by stationary object
If power voltage level is decreased, then power consumption is reduced, but the difference between threshold voltages decreases leading to increased sensing time
Solution Approach 1:
The patent changes the sensing mechanism to work effectively at lower voltage levels. By using the bit line as the reference and implementing a differential sensing approach, the circuit maintains sufficient voltage difference for reliable sensing even when operating at reduced power voltage levels, thus avoiding increased sensing time.
Solution Approach 2:
The patent replaces the traditional high-voltage threshold comparison mechanism with a differential voltage sensing approach. This substitution allows the circuit to operate effectively at lower voltage levels by comparing voltage differences rather than relying on absolute threshold voltage differences, thereby maintaining fast sensing times at reduced power consumption.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables high-speed data reading and reduced current consumption by eliminating the need for a reference cell transistor, maintaining data integrity even at lower power voltage levels.
Implementation Method 1
a sensing unit including first cross-coupled MOS transistors to sense and amplify a voltage difference between a first node and a second node
Implementation Method 2
a unit cell including second cross-coupled cell MOS transistors to latch data and output a first signal and a second signal corresponding to the latched data
Data Source
AI summary
A semiconductor memory device is capable of reading data at a high speed, without using a reference cell transistor. The semiconductor memory device includes a sensing unit including first cross-coupled MOS transistors to sense and amplify a voltage difference between a first node and a second node, and a unit cell including second cross-coupled cell MOS transistors to latch data and output a first signal and a second signal corresponding to the latched data to the first node and the second node, respectively.