EEPROM Programming via Unselected Cell Gate Voltage Control
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Solution Overview
Problem
Conventional split-voltage programming architectures in EEPROM memories face issues with stray programming of unselected cells due to positive word line voltages, leading to data corruption and non-optimum programming conditions.
Innovation Solution
Applying a first nonzero positive voltage to the control gates of unselected memory cells during programming to prevent stray voltages from causing programming operations, allowing for higher word line voltages on unselected rows and optimizing programming conditions without leakage or breakdown issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If positive word line voltages are applied to unselected rows to prevent access transistor leakage and breakdown, then access transistor reliability is improved, but stray programming occurs in unselected memory cells causing data corruption
Solution Approach 1:
The patent applies different voltage levels to different regions: a first positive voltage to control gates of unselected memory cells and a second positive voltage to word lines of unselected rows. This local differentiation allows each region to be optimized for its specific function while preventing harmful interactions between regions.
Solution Approach 2:
The control gates of unselected memory cells act as an intermediary element between the word lines and the floating gates. By applying a specific voltage to these control gates, they mediate the voltage transmission and prevent stray programming currents from reaching the floating gates of unselected cells.
2Reliability
If word line voltage is reduced to prevent stray programming, then data integrity is improved, but access transistor leakage and breakdown issues worsen
Solution Approach 1:
Different voltage levels are applied to different parts of the system: the word lines receive a higher voltage to ensure access transistor reliability, while the control gates of unselected cells receive a specifically controlled voltage to prevent stray programming. This local quality differentiation resolves the contradiction.
Solution Approach 2:
The patent applies a preliminary protective voltage to the control gates of unselected memory cells before stray programming can occur. This preliminary anti-action prevents the harmful effect of stray programming while allowing the word lines to operate at higher voltages for access transistor reliability.
3Volume of moving object
If split-voltage programming is used to reduce coupling factor and programming voltages, then memory cell size is reduced, but stray programming of unselected cells occurs
Solution Approach 1:
The patent maintains the split-voltage architecture for reducing memory cell size while adding local voltage control to the control gates of unselected cells. This local differentiation allows the benefits of split-voltage programming to be retained while eliminating the stray programming issue.
Solution Approach 2:
The control gates of unselected memory cells serve as an intermediary that blocks stray programming currents. This intermediary element allows split-voltage programming to function effectively while preventing harmful currents from reaching the floating gates of unselected cells.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances data storage robustness, reduces the risk of stray programming, and improves long-term reliability by increasing breakdown voltage limits and minimizing gate oxide degradation, while simplifying voltage routing and reducing hot carrier degradations.
Implementation Method 1
The erasure operations and programming operations are implemented by injections of positive or negative charges through the Fowler-Nordheim effect onto the floating gates of the state transistors of the memory cells.
Data Source
AI summary
A method for programming a non-volatile memory (NVM) and an integrated circuit is disclosed. In an embodiment an integrated circuit includes a memory plane organized into rows and columns of memory words, each memory word comprising memory cells and each memory cell including a state transistor having a control gate and a floating gate and write circuitry configured to program a selected memory word during a programming phase by applying a first nonzero positive voltage to control gates of the state transistors of the memory cells that do not belong to the selected memory word.


