Compact EEPROM With Vertical Select Transistor and Split-Voltage Programming
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Solution Overview
Problem
EEPROM memory devices face challenges with high writing voltages that lead to transistor breakdown and premature aging, particularly due to increased leakage and gate oxide breakdown, which complicates fabrication and reduces reliability.
Innovation Solution
A compact EEPROM memory device design that uses a split-voltage programming method with a selection transistor located on the source side, allowing for dense structures and reduced voltage usage, combined with separate source lines for each column of memory words to manage voltage selectively during erase and programming cycles, thereby reducing the risk of spurious erasing and transistor stress.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high programming voltage (13V) is used for EEPROM programming, then programming capability is achieved, but transistor reliability deteriorates due to breakdown and premature aging
Solution Approach 1:
The high programming voltage (Vpp) is segmented into two separate voltage supplies: a positive voltage supply (Vpp+) and a negative voltage supply (Vpp-). This segmentation allows each supply to operate at lower voltage levels, reducing the stress on transistors while maintaining the capability to achieve the required programming voltage difference for Fowler-Nordheim tunneling.
Solution Approach 2:
The invention changes the voltage parameters by introducing separate positive and negative voltage supplies with optimized voltage levels. Instead of using a single high voltage (13V), the system uses Vpp+ and Vpp- with a voltage difference equal to Vpp, allowing transistors to operate at lower individual voltage levels while achieving the required programming effect through the voltage difference.
2Adaptability or versatility
If split-voltage solution with negative voltage is used, then transistor voltage constraint is relaxed, but fabrication process complexity increases due to triple well technology requirement
Solution Approach 1:
The selection transistor serves multiple functions: it acts as a selection device during read operations and as a voltage isolation element during programming operations. This multi-functionality reduces the need for specialized triple well technology while maintaining the benefits of split-voltage operation.
Solution Approach 2:
Instead of using complex triple well technology to handle negative voltages, the invention inverts the approach by using a selection transistor in a specific configuration that naturally handles the voltage splitting without requiring advanced fabrication processes. The selection transistor is positioned and controlled in a way that simplifies the fabrication requirements.
3Adaptability or versatility
If split-voltage solution with negative voltage switching is used, then programming capability is maintained, but memory plane surface area increases due to space-consuming control transistors
Solution Approach 1:
The invention merges the selection function and the voltage control function into a single selection transistor. This consolidation eliminates the need for separate control transistors for negative voltage switching, thereby reducing the surface area required in the memory plane while maintaining full programming capability.
Solution Approach 2:
The selection transistor is designed to perform multiple functions: row selection during read operations and voltage isolation during programming operations. This multi-functionality reduces the overall transistor count and minimizes the surface area required in the memory plane.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables a more reliable and compact EEPROM memory device that operates efficiently at lower voltages, reducing transistor stress and surface area requirements while maintaining bit, byte, or page granularity, and enhancing the memory plane's uniformity and reliability.
Implementation Method 1
The programming or the erasing of a floating-gate transistor consists of the injection or the extraction of electrical charges into or from the gate of the transistor by tunnel effect ('Fowler-Nordheim' effect) by means of a high writing voltage Vpp
Data Source
AI summary
Integrated non-volatile memory device includes an integrated memory cell of the EEPROM type with a floating-gate transistor and a selection transistor connected in series between a source line and a bit line, and a programming circuit for the memory cell. The selection transistor is connected between the floating-gate transistor and the source line. The programming circuit is configured for programming the at least one memory cell with a programming voltage split between a positive voltage and a negative voltage.