EEPROM Write Cycle Optimization via Selective Erasure and Programming
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Solution Overview
Problem
EEPROM memory write operations are hindered by long data transfer times and limited frequency of bus systems, leading to increased consumption and reduced endurance due to the necessity of conventional erasure and programming steps, which can be inefficient for data with specific bit patterns.
Innovation Solution
Implementing a method within the EEPROM device to selectively skip or combine erasure and programming steps based on the bit patterns of the data being written, using internal combinatorial logic to determine if only an erasure or programming step is necessary, thereby accelerating the write cycle and improving endurance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional erasure and programming steps are used for all write operations, then memory reliability is maintained, but write operation duration increases and endurance decreases
Solution Approach 1:
The patent applies partial action by selectively performing only the necessary step (erasure or programming) based on the bit pattern of data to be written. When writing to already erased locations (0x00), only programming is needed. When writing to already programmed locations (0xFF), only erasure is needed. This partial approach maintains reliability by performing required steps while avoiding unnecessary operations that would increase duration and reduce endurance.
Solution Approach 2:
The patent changes the operational parameters of the write cycle by dynamically selecting between different write modes (full erasure+programming, erasure only, programming only, or no operation) based on the data pattern. This parameter change allows the system to adapt the write operation duration and intensity to match the actual needs, resolving the contradiction between maintaining reliability and reducing operation duration.
2Reliability
If erasure and programming steps are performed for every write operation, then data integrity is ensured, but memory endurance deteriorates due to increased write cycles
Solution Approach 1:
The patent implements partial action by performing only the minimal necessary operation to achieve the desired write state. By analyzing the target data pattern, the system determines whether erasure, programming, both, or neither is needed. This reduces the total number of write cycles performed on the memory, thereby improving endurance while maintaining data integrity through selective application of erasure and programming steps.
Solution Approach 2:
The memory device performs self-service by automatically analyzing the data pattern to be written and autonomously selecting the appropriate write mode without external intervention. The control circuitry within the memory device itself determines the optimal write strategy, reducing unnecessary operations and improving endurance while ensuring data integrity through intelligent self-management of the write process.
3Reliability
If full write cycles are executed for all data patterns, then over-programming is prevented, but write operation efficiency decreases
Solution Approach 1:
The patent applies partial action by executing only the necessary portion of the write cycle based on the data pattern. For 0x00 patterns, only programming is performed. For 0xFF patterns, only erasure is performed. For mixed patterns, selective programming is applied. This prevents over-programming by avoiding unnecessary operations while significantly improving write operation efficiency by reducing the total number of steps executed.
Solution Approach 2:
The patent changes the write operation parameters dynamically based on the data pattern being written. The control circuitry adjusts the write cycle configuration (full cycle, erasure only, programming only, or selective programming) to match the specific requirements of each write operation. This parameter adaptation maintains over-programming prevention while optimizing write efficiency for different data patterns.
4Speed
If bus frequency is increased to reduce data transfer time, then transfer speed improves, but for I2C buses maximum frequency is limited to 1 MHz due to speed/consumption compromise
Solution Approach 1:
The patent extracts the bottleneck from the data transfer system by reducing the duration of the write operation itself. Instead of increasing bus frequency to improve transfer speed, the invention shortens the write cycle duration by eliminating unnecessary erasure or programming steps. This approach improves overall data transfer efficiency by reducing the time the bus must remain active, thereby reducing bus consumption without requiring higher frequencies.
Solution Approach 2:
The patent performs preliminary action by analyzing the data pattern before initiating the write operation. The control circuitry evaluates the target data and determines the optimal write strategy in advance. This preliminary analysis allows the system to prepare the minimal necessary write sequence, reducing the overall write duration and bus activity time, thereby improving transfer efficiency without increasing bus frequency or consumption.
Data Source
AI summary
According to one mode of implementation it is proposed to automatically accelerate the write operation by deleting on the basis of the values of the data to be written and optionally on the basis of the values of the data present in the memory the erasure step or the programming step, so doing while optionally using a conventional write command. When the memory is equipped with an error-correcting code based on a Hamming code, a property of the latter makes it possible readily to implement this possible acceleration of the cycles of writings within the memory. This property is that according to which when all the bits of the bytes of a digital word grouping together n bytes are equal to zero, the check bits associated with these bytes are also all equal to zero.