Effective Address Instruction Fetch Unit for Out-of-Order Processors
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Solution Overview
Problem
In out-of-order processors, tracking and translating effective addresses (EAs) for instruction fetches is costly in terms of chip area and power consumption, especially in multithreaded environments where numerous instructions from different address ranges are processed simultaneously.
Innovation Solution
Implementing an effective address (EA) based instruction fetch unit that uses an instruction directory containing EAs instead of real addresses, and an effective-real address table (ERT) that stores both EA-to-RA and RA-to-EA translations only for cache misses, reducing the need for frequent address translations and chip area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If an effective-to-real address table (ERAT) is used in the L1 instruction cache complex, then address translation can be performed, but chip area and power consumption increase
Solution Approach 1:
The patent extracts the address translation function from the L1 instruction cache complex by removing the ERAT. Instead, address translation is performed only when instructions are fetched from main memory, not for every cache access. This separates the address translation operation from the cache structure, reducing chip area while maintaining the necessary address translation capability.
Solution Approach 2:
The patent performs address translation in advance when instructions are initially fetched from main memory into the L1 cache. The effective address is translated to a real address at this preliminary stage, and the translated real address is stored in the cache. Subsequent cache accesses use the stored real address directly without requiring additional translation, thus eliminating the need for a persistent ERAT structure.
2Adaptability or versatility
If an effective-to-real address table (ERAT) is used in the L1 instruction cache complex, then address translation can be performed, but power consumption increases
Solution Approach 1:
The patent removes the ERAT from the L1 instruction cache complex, extracting the address translation function from the cache operation. This eliminates the continuous power consumption associated with maintaining and accessing the ERAT structure for every instruction fetch, while preserving address translation capability when needed through alternative mechanisms.
Solution Approach 2:
Address translation is performed as a preliminary action when instructions are initially loaded into the L1 cache from main memory. The effective address is converted to a real address at this initial stage, and the result is stored for subsequent use. This preliminary translation avoids repeated power-consuming translation operations for every cache access, significantly reducing overall power consumption.
3Reliability
If address translations are performed for every instruction fetch, then correct instructions are retrieved, but unnecessary translations increase power consumption and chip area
Solution Approach 1:
The patent performs address translation as a preliminary action only when instructions are initially fetched from main memory into the L1 cache. The effective address is translated to a real address at this stage, and the translated address is stored in the cache along with the instructions. Subsequent instruction fetches from the L1 cache use the stored real addresses directly without requiring additional translation operations, ensuring both retrieval accuracy and energy efficiency.
Solution Approach 2:
The L1 instruction cache acts as an intermediary structure that stores instructions along with their translated real addresses. This intermediary cache breaks the direct chain between effective address generation and address translation, allowing translations to be performed only when necessary (on initial cache fill) rather than for every instruction fetch, thus reducing power consumption while maintaining reliability.
Data Source
AI summary
Aspects of the invention include a computer-implemented method for executing one or more instructions by a processing unit. The method includes receiving, by an instruction fetch unit (IFU), a request to fetch an instruction for execution, wherein the instruction includes an effective address (EA). The IFU can further access an instruction cache directory (I-directory) using the EA of the requested instruction to determine whether the EA of the requested instruction matches an EA stored in an associated instruction cache (I-cache). An instruction cache (I-cache) can output the requested instruction in response to or based at least in part on determining that the requested instruction EA matches an entry in the I-cache. A decode unit can decode the requested instruction output by the I-cache.