Effective Contact Width Tables for Parasitic Capacitance Extraction
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Solution Overview
Problem
Existing methods for extracting parasitic capacitance in ultra-large scale integrated circuits lack accuracy, particularly for contact and via structures, leading to discrepancies between simulated and actual circuit performance due to ignoring actual shape and size variations.
Innovation Solution
A method involving the creation of technology files with 'Effective Contact Width' and 'Effective via Width' tables, calibrated to match actual contact and via configurations, allowing for precise parasitic capacitance extraction using existing polygon-based tools.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If existing polygon-based extraction tools are used with standard capacitance tables, then extraction speed and ease of operation are maintained, but measurement precision and manufacturing precision of parasitic capacitance extraction deteriorate due to ignoring actual contact and via shape variations
Solution Approach 1:
The patent transforms the extraction methodology by changing the parameter representation from ideal polygon dimensions to effective dimensions that account for actual contact and via shape variations. Effective contact width and effective via width are introduced as new parameters that capture the real-world geometry effects, allowing accurate capacitance extraction while maintaining compatibility with existing polygon-based tools through updated technology files.
Solution Approach 2:
The patent introduces effective contact width and effective via width as intermediary parameters that bridge the gap between ideal polygon representations and actual physical structures. These effective dimensions serve as mediators that translate complex real-world geometry into simplified parameters that can be used with existing extraction tools, resolving the contradiction between accuracy and tool compatibility.
2Ease of manufacture
If ideal polygon shapes are assumed for contacts and vias, then device complexity and ease of manufacture are improved, but measurement precision of parasitic capacitance deteriorates due to shape and size variations being ignored
Solution Approach 1:
The patent modifies the extraction approach by changing from using ideal polygon dimensions to using effective dimensions that incorporate actual contact and via shape characteristics. This parameter transformation allows the extraction process to remain simple and automated while achieving higher accuracy by accounting for real-world geometry variations in the effective width parameters.
3Measurement precision
If actual contact and via shape variations are accounted for, then measurement precision of parasitic capacitance is improved, but device complexity increases due to requiring new extraction methodologies
Solution Approach 1:
The patent introduces effective contact width and effective via width as intermediary parameters that enable accurate capacitance extraction without requiring changes to existing polygon-based extraction tools. These effective dimensions act as intermediaries that encapsulate complex shape variations into single parameters, maintaining tool usability while improving measurement precision.
Solution Approach 2:
The patent creates updated technology files that contain capacitance tables based on effective dimensions, which are copies adapted from standard technology files. These updated files allow existing extraction tools to operate unchanged while producing more accurate results by using the effective width parameters instead of ideal polygon dimensions.
Data Source
AI summary
A system and method for extracting the parasitic contact/via capacitance in an integrated circuit are provided. Parasitic extraction using this system can lead to an improved accuracy on contact/via parasitic capacitance extraction by taking into account of the actual contact/via shape and size variation. The common feature of the various embodiments includes the step of generating a technology file, in which the contact/via capacitance in the capacitance table is derived from an effective contact/via width table. Each element of the effective contact/via width table is calibrated to have a parasitic capacitance matching to that of an actual contact/via configuration occurring in an IC.


