Electrostatically Formed Nanowire Transistors for Threshold Logic
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current CMOS technology faces limitations in scaling for computing, requiring large numbers of transistors and inefficient logic cascading, which hinders the development of complex circuits and increases power dissipation.
Innovation Solution
The use of electrostatically formed nanowire (EFN) transistors with independently controlled gates allows for efficient computation by leveraging threshold logic, reducing the number of transistors needed and enabling complex logic functions with fewer devices, potentially replacing or complementing CMOS technology.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If CMOS technology is used for computing, then transistors can regulate current and voltage flow effectively, but the number of transistors required becomes very large and power dissipation increases
Solution Approach 1:
The patent changes the fundamental operating parameters from conventional CMOS voltage switching to threshold logic with weighted sums. By using multiple gates on single transistors that can be independently biased, the system achieves logic functions with fewer transistors while reducing power dissipation through more efficient voltage utilization and fewer switching events.
Solution Approach 2:
The patent makes transistors multi-functional by equipping them with multiple gates (e.g., four gates per transistor) that can perform different functions simultaneously. A single transistor can participate in multiple logic operations through its multiple gates, reducing the total transistor count needed for complex computing functions while maintaining reliability.
2Adaptability or versatility
If CMOS technology is used for complex circuits, then current switching can be achieved, but the circuit complexity and number of transistors increase significantly
Solution Approach 1:
The patent merges multiple logic functions into fewer transistors by using threshold logic gates where multiple inputs are combined through weighted sums. Instead of requiring separate transistors for each logic operation as in CMOS, the invention combines multiple logic functions within a smaller transistor network that uses shared components and common biasing schemes.
Solution Approach 2:
The patent adds a new dimension to transistor operation by introducing multiple independently controllable gates on each transistor. This dimensional expansion allows a single transistor to participate in multiple logic operations simultaneously, effectively reducing the transistor count needed for complex circuits while maintaining full logic functionality.
3Adaptability or versatility
If more transistors are used in CMOS circuits, then more logic functions can be implemented, but manufacturing cost and device area increase
Solution Approach 1:
The patent merges multiple logic functions into fewer transistors by using threshold logic gates where multiple inputs are combined through weighted sums. Instead of requiring separate transistors for each logic operation as in CMOS, the invention combines multiple logic functions within a smaller transistor network that uses shared components and common biasing schemes.
Solution Approach 2:
The patent makes transistors multi-functional by equipping them with multiple gates (e.g., four gates per transistor) that can be independently biased. A single transistor can participate in multiple logic operations through its multiple gates, reducing the total transistor count needed for complex computing functions while maintaining reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
EFN transistors achieve higher computing efficiency, reduce power consumption, and increase performance by enabling complex logic functions with fewer transistors, offering a more compact and cost-effective alternative for next-generation computing.
Implementation Method 1
The gates inducing a channel in the doped silicon region
Data Source
AI summary
An electrostatically formed nanowire transistor, includes a source, a drain, and multiple gates surrounding a doped silicon region. The gates include a top gate, a bottom gate, and side gates. The gates induce a channel in said doped silicon region. The channel has a width which is decreased by negative biasing of the side gates, and a height and vertical position controlled by the top and bottom gates.