Embedded FPGA Logic Block Abutment for Area-Efficient Interconnect
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Solution Overview
Problem
Existing embedded field programmable gate arrays (EFPGAs) face challenges in optimizing silicon area utilization and accurately simulating timing delays due to the use of single-type configurable logic blocks and dedicated routing channels, which are time-consuming and inefficient.
Innovation Solution
Implementing a hierarchical EFPGA design using multiple abuttable configurable logic blocks (ACLBs) that interconnect through pin assignment and alignment, eliminating the need for dedicated routing channels and allowing for flexible, scalable, and predictable performance by achieving connectivity through abutment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If dedicated routing channels are used to interconnect configurable logic blocks, then connectivity between blocks is achieved, but silicon area is substantially consumed by routing channels
Solution Approach 1:
The patent merges the logic block functionality with interconnection capability by enabling direct abutment between adjacent logic blocks. The abutment mechanism integrates what were previously separate entities (logic blocks and routing channels) into a unified structure where connection is inherent to the physical arrangement, eliminating the need for dedicated routing channels and reducing silicon area consumption.
Solution Approach 2:
The patent extracts the dedicated routing channels from the system entirely. Instead of having separate routing infrastructure, the interconnection function is achieved through the abutment of adjacent logic blocks themselves, removing the harmful element (routing channels consuming area) while preserving the useful function (connectivity).
2Adaptability or versatility
If multiple types of configurable logic blocks are used, then design flexibility is improved, but placement and routing complexity increases
Solution Approach 1:
The patent applies local quality by allowing different types of logic blocks to be placed at different locations in the array based on specific design requirements. Each block type can be optimally positioned where its functionality is most needed, while the standardized abutment interface ensures that regardless of type, blocks connect uniformly to adjacent blocks, maintaining simplicity in the interconnection mechanism.
Solution Approach 2:
The abutment mechanism serves as a universal interface that works with all types of logic blocks. This multi-functional connection method eliminates the need for different routing mechanisms for different block types, reducing overall system complexity while supporting design flexibility through block type diversity.
3Measurement precision
If wire lengths and switch counts are determined after placement and routing, then actual circuit performance is known, but design simulation and timing analysis cannot be performed beforehand
Solution Approach 1:
The patent enables preliminary timing simulation and performance analysis by determining wire lengths and switch counts during the placement phase itself, rather than after routing. The abutment structure allows these parameters to be calculated based on the physical arrangement of blocks before final routing decisions, enabling early design validation and reducing overall design time.
4Adaptability or versatility
If programmable interconnect elements are associated with each logic block, then connectivity is achieved, but area consumption and programming complexity increase
Solution Approach 1:
The abutment mechanism enables logic blocks to establish connections with adjacent blocks through their inherent physical arrangement rather than requiring extensive programmable interconnect elements within each block. The blocks essentially serve their own interconnection needs through the abutment structure, reducing the amount of programmable logic required in each individual block while maintaining connectivity flexibility.
Data Source
AI summary
An embedded field programmable gate array (EFPGA) includes several abuttable configurable logic blocks (ACLBs). Each ACLB is interconnected with adjacent ACLBs by abutment of an out pin to an adjacent in pin. Each ACLB may be an instance of multiple programmable functional blocks. Each ACLB may be a particular ACLB type that provides a particular instance of the multiple programmable functional blocks. The EFPGA may include several ACLBs of the same type. An ACLB of one type may be adjacent an ACLB of a different type. The ACLBs may form sets that are configured identically. The sets may be interconnected by abutment of an out pin to an adjacent in pin. The EFPGA may be part of a system-on-chip integrated circuit. A method for designing an EFPGA with ACLBs that are interconnected by abutment is disclosed.