Embedded FPGA ACLB Layout Without Dedicated Routing Channels
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Solution Overview
Problem
Existing embedded field programmable gate arrays (EFPGAs) face challenges in efficient silicon area utilization and wire length-related delay assessments due to the use of single-type configurable logic blocks and dedicated routing channels for interconnection, which complicates design implementation and timing simulation.
Innovation Solution
The implementation of multiple abuttable configurable logic blocks (ACLBs) that interconnect through pin assignment and alignment, eliminating the need for additional routing channels and allowing hierarchical organization, enabling flexible and scalable EFPGA designs with predictable performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If dedicated routing channels are used for interconnection between configurable logic blocks, then connectivity is achieved, but silicon area is substantially consumed
Solution Approach 1:
The patent merges the logic block functionality with interconnection capabilities by enabling direct abutment between adjacent configurable logic blocks. The shared boundary pins between abutting blocks serve dual purposes: as logic block I/O pins and as interconnection points, eliminating the need for separate dedicated routing channels and thereby reducing silicon area consumption while maintaining connectivity.
Solution Approach 2:
The boundary pins of the configurable logic blocks are designed to serve multiple functions: they act as both the I/O pins for the logic blocks and as the interconnection points for adjacent blocks. This multi-functionality eliminates the need for separate dedicated routing infrastructure, reducing overall silicon area usage while preserving full connectivity capabilities.
2Adaptability or versatility
If multiple types of configurable logic blocks are used, then design flexibility is improved, but design complexity increases
Solution Approach 1:
The patent segments the configurable logic block into standardized functional components (logic elements, multiplexers, and boundary pins) that can be independently configured. This segmentation allows multiple types of logic blocks to be created from the same basic building blocks, providing design flexibility while maintaining a consistent, manageable structure that doesn't excessively increase design complexity.
Solution Approach 2:
The patent enables design flexibility by allowing configuration of logic blocks through parameter changes rather than requiring fundamentally different block structures. The same basic logic block architecture can be customized by changing parameters such as logic function selection, pin assignments, and interconnection configurations, providing versatility without proportionally increasing design complexity.
3Speed
If wire lengths are reduced for interconnection, then delay is reduced, but routing flexibility is limited
Solution Approach 1:
The patent segments the interconnection architecture into direct abutment connections between adjacent logic blocks, eliminating the need for long wire routes through dedicated routing channels. Each logic block is connected directly to its neighbors through shared boundary pins, minimizing wire length and delay while the grid-based abutment structure preserves sufficient routing flexibility for various logic implementations.
Data Source
AI summary
An embedded field programmable gate array (EFPGA) includes several abuttable configurable logic blocks (ACLBs). Each ACLB is interconnected with adjacent ACLBs by abutment of an out pin to an adjacent in pin. Each ACLB may be an instance of multiple programmable functional blocks. Each ACLB may be a particular ACLB type that provides a particular instance of the multiple programmable functional blocks. The EFPGA may include several ACLBs of the same type. An ACLB of one type may be adjacent an ACLB of a different type. The ACLBs may form sets that are configured identically. The sets may be interconnected by abutment of an out pin to an adjacent in pin. The EFPGA may be part of a system-on-chip integrated circuit. A method for designing an EFPGA with ACLBs that are interconnected by abutment is disclosed.