eFPGA Logic Cell Mapping to Cut LUT Memory Growth
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Solution Overview
Problem
Conventional embedded FPGAs (eFPGAs) in ASICs face challenges in reducing logic cell size while maintaining circuit speed, due to the use of SRAM-based LUTs which require large areas and lead to exponential memory requirements with increasing input numbers.
Innovation Solution
A programmable logic circuit with a novel structure that uses basic logic cells with programmable NOT circuits to configure nodes in a gate-level netlist, allowing for flexible input and output switching based on connection relationships, thereby reducing memory requirements and maintaining circuit speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If FFs (Flip-Flops) are used for logic cells in eFPGAs instead of SRAMs, then the device can be integrated into ASICs, but the area required increases several times (6-10 times) compared to SRAM-based FPGAs
Solution Approach 1:
The patent changes the fundamental parameter of memory organization from traditional LUT-based structures to a hypercube-based structure. This parameter change allows the logic cell to achieve higher density by organizing storage resources in a multi-dimensional hypercube configuration, where nodes represent storage elements and edges represent connections, thereby reducing the area required per logic function while maintaining ASIC integrability.
2Speed
If the number of inputs to LUTs is increased to reduce the number of logic levels, then the circuit speed improves, but the number of memories increases exponentially
Solution Approach 1:
The patent transitions from traditional two-dimensional LUT structures to a multi-dimensional hypercube organization. In this hypercube structure, nodes represent storage elements and edges represent connections, enabling the system to accommodate more inputs without exponentially increasing memory count. The dimensional expansion allows efficient routing and connection management, maintaining circuit speed while reducing memory quantity.
3Quantity of substance
If the number of inputs to LUTs is decreased to reduce the number of memories, then the memory requirements decrease, but the number of logic levels increases causing slowdown
Solution Approach 1:
By organizing storage elements in a hypercube structure with nodes and edges, the patent enables efficient multi-path routing that reduces the effective logic levels. The multi-dimensional connectivity allows signals to traverse through multiple parallel paths simultaneously, compensating for the reduced input count per logic element and maintaining overall circuit speed while reducing total memory requirements.
Data Source
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AI summary
In the conventional eFPGAs, there have been two challenges: the first one being size reduction of the logic cells to improve the implemented logic density, and the second one being minimization of the speed difference with the ASIC. According to the present embodiment, there is provided a method for configuring a programmable logic circuit represented by a gate-level netlist, wherein this is done by assigning the gate-level netlist to a 4-input, 3-output combinational logic cell, which is composed of a combination of 3 of 2-input (m-input) basic logic cells, wherein the combinational logic cell covers 3 (n) nodes constituting a graph of the netlist.