eFPGA Lane Architecture for Higher Logic Density
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Solution Overview
Problem
Conventional eFPGAs face challenges in improving logic density due to the use of full crossbar connections and the requirement for a large number of component memories and multiplexers, which limits the implementation of logic cells.
Innovation Solution
A programmable logic circuit with a new wiring architecture that considers signal flow in a netlist, using lanes with programmable logic cells and reduced crossbar connections, along with the use of PAE circuits to enhance logic density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If full crossbar connections are used in eFPGA logic blocks, then wiring flexibility is improved, but the number of component memories and multiplexers increases significantly
Solution Approach 1:
The patent segments the full crossbar connection into multiple lanes, where each lane contains a subset of logic cells connected through localized crossbar structures. This segmentation reduces the global wiring complexity while maintaining flexibility within each lane, directly addressing the contradiction between wiring flexibility and device complexity.
2Area of stationary object
If FFs are used in eFPGA logic cells instead of SRAMs, then area is reduced, but logic density decreases due to larger cell size
Solution Approach 1:
The patent merges multiple logic cells into lanes, allowing shared resources and optimized resource utilization. By combining FF-based logic cells in structured lanes with reduced crossbar connections, the design achieves better area efficiency while maintaining or improving logic density through resource sharing and reduced overhead.
3Adaptability or versatility
If multiple outputs are added to LUTs in eFPGA, then logic functionality is improved, but the number of required FFs increases
Solution Approach 1:
The patent implements multi-output LUTs within the lane structure where a single LUT can serve multiple outputs through the lane's shared crossbar connection. This universal approach allows one LUT to fulfill multiple functional roles, improving logic functionality without proportionally increasing the number of FFs, as outputs can be selectively routed through the lane infrastructure.
Data Source
AI summary
Conventional eFPGAs have a problem of improving implemented logic density, and there is a need for a programmable logic circuit with a new structure capable of solving this problem. There is provided a programmable logic circuit, comprising a plurality of lanes sequentially connected in the programmable logic circuit in a direction of flow of input signals of this programmable logic circuit, wherein each of the plurality of lanes has one or more logic cells, inputs input signals into the lane to each logic cell via a program-controllable input-side selector circuit, and outputs output signals from the each logic cell as input signals into a next sequential lane connected to this lane or/and outputs the output signals as output signals of this programmable logic circuit.