eFPGA Logic Cell Mapping for Higher Density and ASIC-Like Speed
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Solution Overview
Problem
Conventional embedded FPGAs (eFPGAs) in ASICs face challenges in reducing logic cell size to improve logic density and minimizing speed differences with the rest of the ASIC, due to the use of SRAM-based LUTs which require large areas and lead to exponential memory requirements with increasing input numbers.
Innovation Solution
The proposed programmable logic circuit employs a novel structure based on a basic logic cell that includes programmable NOT circuits added to basic logic operation elements, allowing the circuit to switch inputs and outputs based on connection relationships in the gate-level netlist, thereby reducing memory requirements and maintaining circuit speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If FFs (Flip-Flops) are used for logic cells in eFPGAs, then the logic cell can be configured, but the area required increases several times compared to SRAMs, reducing logic density
Solution Approach 1:
The logic cell is segmented into multiple functional blocks including configurable logic blocks (CLBs), input logic blocks (ILBs), and output logic blocks (OLBs). Each block can be independently configured and optimized, allowing the system to achieve high adaptability while minimizing the area of each individual block through specialized design.
Solution Approach 2:
The logic cell design provides universal functionality through configurable logic blocks that can implement various logic functions, along with integrated input and output logic blocks that handle multiple signal routing and buffering functions. This multi-functional approach eliminates the need for separate dedicated blocks, reducing overall area while maintaining configurability.
2Adaptability or versatility
If the number of inputs to LUTs increases, then the logic function capability improves, but the number of memories increases exponentially, increasing area
Solution Approach 1:
The logic cell employs dynamic configuration capabilities where the number and connectivity of logic elements can be adjusted based on the specific logic function requirements. This dynamic reconfigurability allows the system to optimize the balance between logic function capability and memory usage for each specific application, avoiding the exponential memory growth associated with fixed high-input LUTs.
Solution Approach 2:
The patent introduces a new dimensional approach by adding temporal and spatial configuration dimensions to the logic cell architecture. Through multi-cycle configuration and hierarchical organization of logic elements, the system achieves high logic function capability without requiring exponential memory resources, as the configuration space is expanded beyond the traditional single-cycle LUT model.
3Quantity of substance
If the number of inputs to LUTs decreases, then the number of memories reduces, but the number of logic levels increases, causing slowdown
Solution Approach 1:
The logic cell implements a nested hierarchical structure where configurable logic blocks contain multiple logic elements that can be nested within each other. This nesting allows the system to maintain shallow logic levels by organizing functions hierarchically, while using efficient memory structures at each level to minimize the total number of memory resources required.
Solution Approach 2:
The patent introduces intermediary carry chains and inter-block routing structures that act as mediators between logic elements. These intermediaries enable parallel processing and reduce the effective logic path length, maintaining high speed performance even when using fewer memory resources per logic element.
Data Source
AI summary
In the conventional eFPGAs, there have been two challenges: the first one being size reduction of the logic cells to improve the implemented logic density, and the second one being minimization of the speed difference with the ASIC. According to the present embodiment, there is provided a method for configuring a programmable logic circuit represented by a gate-level netlist, wherein this is done by assigning the gate-level netlist to a 4-input, 3-output combinational logic cell, which is composed of a combination of 3 of 2-input (m-input) basic logic cells, wherein the combinational logic cell covers 3(n) nodes constituting a graph of the netlist.