E-fuse Array Circuit Area and Power Optimization
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Solution Overview
Problem
Existing e-fuse circuits face challenges in minimizing area occupancy and improving current consumption efficiency, particularly in programming and reading operations, due to the need for large transistors or amplifiers, which increase complexity and power consumption.
Innovation Solution
The e-fuse array circuit incorporates a high voltage pumping unit, negative voltage pumping unit, program/read lines, row lines, and column circuits to optimize voltage levels, allowing for efficient programming and reading operations by sharing amplifiers and reducing area occupancy through array configuration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a common power source voltage is supplied to the gate of the transistor, then the e-fuse operates as a capacitor with no current flow, but the transistor size must be increased to determine data immediately, increasing area occupancy
Solution Approach 1:
Multiple e-fuse devices are merged into an array configuration where they share common row lines and column lines. The sense amplifier is shared among multiple e-fuses, eliminating the need for individual amplifiers for each device and reducing overall area occupancy while maintaining reliable data determination.
Solution Approach 2:
The e-fuse devices are arranged in a two-dimensional array structure with row and column organization. This dimensional arrangement allows for efficient addressing and sensing of individual e-fuses within the array, reducing the area required compared to linear or individual configurations.
2Reliability
If a high power source voltage is supplied to the gate to rupture the gate oxide and short the gate with drain/source, then the e-fuse operates as a resistor for data storage, but the transistor size must be increased or additional amplifiers must be included, increasing complexity and area
Solution Approach 1:
The program circuitry and sense amplifier are merged into shared resources for the entire e-fuse array. A single sense amplifier serves multiple e-fuses by selectively activating specific row and column lines, dramatically reducing the number of amplifiers needed and simplifying the overall circuit architecture.
Solution Approach 2:
The sense amplifier is designed to serve multiple functions: it can sense the resistance state of multiple e-fuses and work with different voltage levels for both read and program operations. This multi-functionality eliminates the need for separate amplifiers for different operations, reducing device complexity.
3Measurement precision
If individual amplifiers are included in each e-fuse to sense current flow, then data can be sensed accurately, but the area occupancy and current consumption increase significantly
Solution Approach 1:
Instead of having individual amplifiers for each e-fuse, the invention merges multiple sensing functions into a single shared sense amplifier. The amplifier selectively senses current from specific e-fuses by activating corresponding row and column lines, maintaining measurement precision while dramatically reducing the total area required.
Solution Approach 2:
The sensing architecture transitions from a one-to-one mapping (individual amplifier per e-fuse) to a many-to-one relationship where one amplifier serves many e-fuses. This is achieved through the two-dimensional array organization with row and column selective activation, reducing amplifier area while preserving sensing accuracy.
4Productivity
If voltage levels are not optimized in the e-fuse circuit, then programming and reading operations can be performed, but current consumption efficiency is poor
Solution Approach 1:
The circuit employs optimized voltage levels for different operations: a first voltage level for program operations and a second, lower voltage level for read operations. This parameter change allows the e-fuse to be programmed with sufficient voltage to rupture the gate oxide while consuming minimal current during read operations, improving overall current consumption efficiency.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration minimizes area usage and enhances current consumption efficiency by optimizing voltage levels, enabling efficient data storage and retrieval in e-fuse arrays, suitable for applications in DRAM chips and various IC chips.
Implementation Method 1
a high voltage pumping unit configured to generate a high voltage by pumping a power source voltage
Implementation Method 2
a negative voltage pumping unit configured to generate a negative voltage by pumping a ground voltage
Implementation Method 3
If a high power source voltage that the transistor T may not tolerate is supplied to the gate G, the gate oxide of the transistor T is ruptured, and the gate G and the drain/source D/S are shorted
Data Source
AI summary
An e-fuse array circuit includes a high voltage pumping unit configured to generate a high voltage by pumping a power source voltage, a negative voltage pumping unit configured to generate a negative voltage by pumping a ground voltage, a program/read line supplied with the high voltage when a program operation is activated, a read voltage, which is lower than the high voltage, when a read operation is activated, or the negative voltage when deactivated, a row line supplied with the ground voltage when the row line is activated or the negative voltage when the row line is deactivated, an e-fuse device supplied with voltage of the program/read line, a switch device controlled by the row line and configured to electrically connect the e-fuse device with a column line, and a column circuit configured to supply the negative voltage to the column line when the column line is activated.