eFuse Cell Array Asymmetric Layout for Leakage Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In very large scale integrated circuits, electronic fuses (eFuses) require a large programming current to create an open circuit, leading to increased chip area and a desire for a compact design of non-volatile memory devices.
Innovation Solution
The eFuse cell array design includes a first and second unit cell with reversed placement orders of PN diodes, cell read transistors, and fuse elements, along with shared read and program transistors, to reduce the footprint and prevent leakage current damage between adjacent cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a large programming current is used to program the eFuse, then the eFuse can be programmed to create an open circuit, but the chip area increases due to the requirement for MOS transistors with large channel width
Solution Approach 1:
The patent merges the programming function and reading function into a single shared transistor, eliminating the need for separate large-channel-width MOS transistors for programming. This consolidation allows the eFuse cell to achieve programming capability without proportionally increasing chip area, as the shared transistor serves dual purposes.
Solution Approach 2:
The shared transistor is designed to perform multiple functions: it acts as the programming transistor during programming operations and as the read transistor during read operations. This multi-functionality reduces the total transistor count and eliminates redundant circuitry, thereby reducing chip area while maintaining full eFuse programming and reading capabilities.
2Area of stationary object
If adjacent eFuse cells are placed close together to reduce footprint, then chip area decreases, but leakage current between adjacent cells increases causing damage
Solution Approach 1:
The patent introduces asymmetric layout techniques where adjacent eFuse cells are positioned at non-uniform distances from each other. Specifically, alternating rows or columns of cells are placed at different spacing intervals, which disrupts the symmetry of leakage current paths and reduces the cumulative leakage effect between adjacent cells while maintaining compact overall footprint.
Solution Approach 2:
The patent introduces intermediate isolation structures (such as dummy transistors, isolation trenches, or guard rings) placed between adjacent eFuse cells. These intermediary elements act as barriers to leakage current, preventing direct coupling between neighboring cells and reducing leakage-induced damage while allowing cells to remain closely spaced for area efficiency.
3Area of stationary object
If the eFuse cell footprint is reduced for compact design, then chip area decreases, but design rule satisfaction becomes more difficult to achieve
Solution Approach 1:
The patent segments the eFuse cell into modular functional blocks (programming transistor, read transistor, fuse element, isolation regions) that can be independently optimized and arranged. This segmentation allows each component to be sized and positioned to meet minimum design rules while the overall cell footprint is minimized through efficient packing of these modular units.
Solution Approach 2:
The patent employs multi-dimensional layout strategies, utilizing both horizontal and vertical spacing to satisfy design rules. By arranging components in two dimensions and using vertical isolation techniques (such as deep trenches or stacked configurations), the design achieves compact footprint while maintaining required spacing and isolation distances to satisfy manufacturing design rules.
Data Source
AI summary
An eFuse cell array includes a first unit cell and a second unit cell, each including a PN diode, a cell read transistor, and a fuse element. A first placement order of the PN diode, the cell read transistor, and the fuse element in the first unit cell is reversed with respect to a second placement order of the PN diode, the cell read transistor, and the fuse element in the second unit cell.