eFuse Cell Backside Power Rails for Low-Resistance Programming
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing eFuse devices in IC chips face challenges due to high resistance in vias transmitting power from the backside to the frontside, making it difficult to program IC components effectively.
Innovation Solution
Implementing eFuse cells with backside power rails and via structures to reduce resistance and power dissipation by providing supply voltage from the backside, using backside metallization layers and incorporating additional via structures to optimize the conduction path.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If power is transmitted from the backside to the frontside through vias, then the eFuse cells can be programmed, but the resistance in the vias is high making programming difficult
Solution Approach 1:
The patent transitions from traditional frontside-only power delivery to backside power delivery through vias, utilizing the vertical dimension to route power rails from the opposite side of the substrate. This dimensional change allows power to be delivered through a different path, enabling the use of backside metallization layers that can provide lower resistance connections when properly configured with multiple via structures and optimized metallization patterns.
2Reliability
If additional via structures and backside metallization layers are incorporated, then resistance is reduced and programming efficiency improves, but device complexity increases
Solution Approach 1:
The patent combines multiple via structures with backside metallization layers to create an integrated power delivery system. By merging these components into a unified backside power rail architecture, the design achieves reduced resistance through parallel conduction paths while managing complexity through systematic integration of the via and metallization elements into a coordinated structure.
Solution Approach 2:
The backside metallization layers serve multiple functions: they act as power rails for eFuse programming, provide structural support, and enable routing of power to multiple eFuse cells simultaneously. This multi-functionality reduces the need for separate dedicated structures, thereby managing complexity while achieving the desired electrical performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces resistance and improves programming efficiency of eFuse cells, enhancing flexibility in IC design and manufacturing processes.
Implementation Method 1
a plurality of first via structures coupling one or more second portions of the first active region to the second interconnect structure
Data Source
AI summary
A memory device includes a memory cell having a transistor and a resistor coupled to each other, where the memory cell is on the first side, and the transistor further includes a plurality of first sub-transistors disposed in a first region of the substate. The memory device includes a plurality of second sub-transistors disposed in a second region of the substrate. The memory device further includes a first interconnect structure disposed on the second side. The first sub-transistors are each coupled to the first interconnect structure through a plurality of first via structures. The second sub-transistors are each coupled to the first interconnect structure through a plurality of second via structures and at least a third via structure, where the first via structures and the second via structures each have a first cross-sectional area, and the third via structure has a second cross-sectional area that is different from the first cross-sectional area.