Efuse Bit Cell With SRAM Latch For Fast Readout
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Solution Overview
Problem
The integration level of SRAMs is low, and they cannot save data when power is off, leading to long system powering-up times in integrated chips due to slow NMOS transistor switching speeds and large area occupancy, which affects user experience in devices like cellular phones and laptops.
Innovation Solution
The Efuse bit cell design includes a data latch with a fuse and resistor in separate branches, a selection controller, diodes for write signals, and a pass unit for high readout speed, allowing synchronization with the system clock and reducing area occupancy by using a 4T latch structure and diodes to manage data latching and transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If a large-size NMOS transistor is used to provide sufficient programming current for the fuse, then the programming capability is improved, but the switching speed deteriorates due to large drain-gate load capacitance
Solution Approach 1:
The patent divides the single large NMOS transistor into multiple smaller NMOS transistors connected in parallel. This segmentation allows the total programming current to be distributed across multiple devices, reducing the drain-gate load capacitance of each individual transistor while maintaining the overall current capability. The smaller transistors switch faster due to reduced gate capacitance, resolving the contradiction between programming current and switching speed.
2Speed
If SRAM is used for high read speed, then the read performance is improved, but the integration level deteriorates and data cannot be saved when power is off
Solution Approach 1:
The patent merges the Efuse memory cell structure with SRAM latching circuits to create an integrated structure. The Efuse cell incorporates SRAM-like latch circuits that can rapidly read the fuse state, combining the non-volatile storage capability of Efuse with the fast read performance of SRAM. This integration improves read speed while maintaining data persistence when power is off, and optimizes the overall integration level by unifying the memory cell design.
3Speed
If the NMOS transistor size is reduced to improve switching speed, then the switching performance is improved, but the programming current capability deteriorates
Solution Approach 1:
The patent segments the total programming current requirement across multiple smaller NMOS transistors connected in parallel. Each transistor has reduced size for faster switching, but their combined parallel configuration delivers the necessary total programming current. This segmentation strategy simultaneously achieves both fast switching speed and sufficient current capability.
Solution Approach 2:
The patent designs the NMOS transistor array to serve multiple functions: individual transistors provide fast switching for signal propagation, while their parallel combination delivers high programming current. The same transistor structure fulfills both speed and current requirements through multi-functional operation.
4Area of stationary object
If traditional Efuse cell structure is used, then the area occupancy is reduced, but the read speed deteriorates and cannot synchronize with system clock
Solution Approach 1:
The patent merges Efuse cell structure with SRAM latch circuits in an integrated design. This combination enables the memory cell to maintain compact area occupancy while achieving SRAM-like fast read speeds that can synchronize with the system clock. The unified structure eliminates the need for separate Efuse and SRAM blocks, optimizing both area and performance.
Solution Approach 2:
The patent introduces dynamic control mechanisms including word line signals and pass transistors that enable rapid data transmission from the fuse to the output. These dynamic elements allow the cell to switch states quickly and synchronize with the system clock, transforming the traditionally slow Efuse read operation into a high-speed operation while maintaining area efficiency.
Data Source
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AI summary
The present invention provides Efuse bit cells and read/write methods thereof, and Efuse arrays. An exemplary Efuse bit cell includes a data latch configured to latch data of the Efuse bit cell, having two branches with a fuse disposed in a first branch and a resistor disposed in a second branch; a selection controller configured to control connections between one terminal of the first branch and a power source and between one terminal of the second branch and the power source, another terminal of the first branch and another terminal of the second branch being connected to ground; a first diode and a second diode, one of the first diode and the second diode being configured to input a write data signal; and a pass unit configured to transmit data stored in the Efuse bit cell and output a bit line signal.