Efuse Circuit Dynamic Burn Control and Area Reduction
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Solution Overview
Problem
Conventional efuse circuits in memory devices face issues with increased chip area due to the use of a 'use bit' for checking burned efuses, processing speed degradation due to extended wait times for burn voltage recovery, and reliability degradation from overwrite operations between power on and off, as well as from simultaneous burning of multiple efuses.
Innovation Solution
An efuse circuit and operation method that determine whether efuses are burned without a 'use bit', using a control circuit to detect efuse sets and disable overwrite operations on burned efuses, thereby reducing chip area and improving processing speed and reliability by dynamically adjusting wait times based on detection signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a use bit is used to check whether an efuse set has a burned efuse, then the burn operation reliability is improved, but the chip area increases
Solution Approach 1:
The patent extracts and removes the use bit from the efuse circuit structure. Instead of using a dedicated use bit to track burned efuses, the invention uses the existing detection mechanism to determine burn status, thereby eliminating the additional chip area requirement while maintaining burn operation reliability through the control circuit's ability to detect and manage burned efuses
Solution Approach 2:
The detection circuit is designed to serve multiple functions: it detects both normal efuse states and burned efuse states, and provides this information to the control circuit which then manages the burn operation accordingly. This multi-functionality eliminates the need for separate use bits while maintaining reliability
2Reliability
If the wait time of burn clock signal is extended to wait for burn voltage recovery, then the burn operation reliability is improved, but the processing speed degrades
Solution Approach 1:
The patent implements dynamic wait time adjustment based on the actual burn voltage recovery status. The control circuit monitors the burn voltage and adjusts the wait time of the burn clock signal dynamically - extending it only when necessary for voltage recovery while minimizing delays when voltage recovers quickly, thus balancing reliability and processing speed
Solution Approach 2:
The detection circuit provides feedback about the burn voltage status to the control circuit, which then adjusts the burn clock signal timing accordingly. This feedback mechanism ensures that wait times are optimized based on actual voltage recovery conditions rather than using fixed conservative delays
3Adaptability or versatility
If overwrite operation is allowed on efuse set having burned efuse between power on and off, then the data update flexibility is improved, but the burn operation reliability degrades
Solution Approach 1:
The control circuit acts as an intermediary between the detection circuit and the efuse write operation. It receives detection results about burned efuses and uses this information to control whether overwrite operations are permitted, thereby protecting burn operation reliability while maintaining data update flexibility for non-burned efuses through intelligent mediation
4Productivity
If multiple efuses are burned simultaneously, then the productivity is improved, but the burn operation reliability degrades due to voltage pull-down
Solution Approach 1:
The control circuit dynamically manages the burning process by monitoring voltage levels and adjusting which efuses are burned at what time. When multiple efuses need to be burned, the system dynamically schedules them in sequences or groups based on voltage recovery status, maximizing throughput while preventing reliability degradation from excessive simultaneous burning
Solution Approach 2:
The patent implements periodic burning cycles where efuses are burned in controlled batches with intermediate waiting periods for voltage recovery. This periodic action pattern allows high productivity through parallel processing capability while ensuring reliability by allowing voltage recovery between burning cycles
Data Source
AI summary
An efuse circuit adapted for a memory device is provided. The efuse circuit includes a plurality of efuse sets and a control circuit. Each of the plurality of efuse sets includes a plurality of efuses. When a power is turned on, the control circuit detects each of the plurality of efuse sets to generate a detection signal. The control circuit determines whether the efuses of each of the efuse sets are burned according to the detection signal to determine whether to perform a burn operation on the plurality of efuses. When the control circuit determines that at least one of the plurality of efuses is a burned efuse according to the detection signal, the control circuit latches a write data of at least one burned efuse and disables an overwrite operation on the efuse set to which the at least one burned efuse belongs.