Integrated Circuit E-Fuse Compression for Secure Capability Configuration
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Solution Overview
Problem
Existing electronic fuse implementations require multiple physical fuse bits to store configuration information, leading to large circuit sizes and increased manufacturing costs due to the need for more silicon area and longer verification cycles.
Innovation Solution
An integrated circuit comprising a non-volatile memory circuit, a programmable memory circuit, and a decision circuit that uses data compression and comparison operations to equivalently represent multiple capability bits with fewer physical bits, reducing the E-Fuse array size and enabling post-fabrication configuration of system capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple physical fuse bits are used to store configuration information, then the reliability and security of capability configuration is improved, but the circuit area and manufacturing complexity increase
Solution Approach 1:
The patent uses a cryptographic key derivation mechanism where a small number of physical fuse bits (e.g., 64 bits) are used to generate a larger configuration space (e.g., 1024 capability bits) through cryptographic functions. This allows the system to securely configure many more capabilities than the number of physical bits would suggest, effectively creating a cryptographic copy that expands the configuration space without proportionally increasing physical area.
Solution Approach 2:
The patent implements a universal configuration mechanism where a single set of physical fuse bits serves multiple purposes: storing security credentials, generating cryptographic keys, deriving capability configurations, and enabling post-fabrication reconfiguration. This multi-functional approach allows the same physical bits to secure and configure the entire system, eliminating the need for separate dedicated bits for each capability.
2Adaptability or versatility
If multiple physical fuse bits are used to store configuration information, then the configuration capability is improved, but the manufacturing verification time increases
Solution Approach 1:
The patent derives a large configuration space from a small set of physical fuse bits using cryptographic key derivation. Instead of verifying each individual capability bit separately (which would take time proportional to the number of capabilities), the system verifies the cryptographic derivation once, then automatically generates all capability configurations from that single verification, dramatically reducing manufacturing verification time.
Solution Approach 2:
The patent performs cryptographic key derivation and capability configuration generation during the fabrication process itself, before the product reaches the customer. The physical fuse bits are programmed with cryptographic keys during manufacturing, and the capability configurations are pre-derived and stored in non-volatile memory, so that no time-consuming verification or configuration is needed after fabrication.
3Area of stationary object
If fewer physical fuse bits are used, then the circuit area is reduced, but the information storage capacity decreases
Solution Approach 1:
The patent changes the informational density of the physical fuse bits by using cryptographic functions. Instead of each bit directly representing one capability (1:1 mapping), the system uses cryptographic key derivation to expand the information content. For example, 64 physical bits can securely configure 1024 capabilities through cryptographic expansion, achieving a 16:1 effective ratio rather than a 1:1 ratio.
Solution Approach 2:
The patent creates cryptographic copies and derivatives of the physical fuse bit data. The physical bits store a cryptographic key, which is then used to generate multiple capability configurations through cryptographic functions. This copying and derivation process allows a small amount of physical data to represent and control a much larger configuration space.
Data Source
AI summary
A method of integrated circuit includes: providing a non-volatile memory circuit for securely and permanently recording and protecting key data content having Y bits; providing a programmable memory circuit for storing user configuration data content having X bits greater than Y bits; converting the user configuration data content having X bits into user configuration key content having Y bits; comparing the user configuration key content having Y bits with the key data content having Y bits; selecting fallback configuration data content having X bits as output data when the user configuration key content does not match the key data content; selecting the user configuration data content having X bits as the output data when the user configuration key content matches the key data content; and receiving the output data of the decision circuit and performing at least one corresponding capability operation according to the output data.