E-fuse Circuit Multi-mode Latch Area Reduction
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Solution Overview
Problem
Conventional E-fuse circuits require a large area due to the need for numerous latches and complex decoders to manage redundant memory cells, which increases with higher memory cell density.
Innovation Solution
An E-fuse circuit design that shares latch and logic circuits between normal and burn-in modes, replacing the decoder with simpler logic circuits to reduce circuit area and complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of redundant memory cells and E-fuses is increased to handle higher memory cell density, then the memory capacity and fault tolerance are improved, but the required circuit area increases due to more latch circuits and decoders
Solution Approach 1:
The latch circuit is designed to perform dual functions: in burn-in mode, it temporarily stores selection signals for E-fuse programming; in normal mode, it stores address data for comparison with damaged memory cell addresses. This multi-functionality eliminates the need for separate latch circuits for different operational modes, reducing overall circuit area while supporting increased memory density and redundant cell capacity.
Solution Approach 2:
The patent combines the selection signal generation logic and address comparison logic into a unified logic circuit structure. The logic circuit generates selection signals during burn-in mode and performs address comparison during normal mode, merging functions that were previously handled by separate decoder circuits. This consolidation reduces the total number of logic components and decreases circuit area.
2Measurement precision
If a decoder with complex logic design is used to select E-fuses and generate selection signals, then the accuracy of damaged memory cell identification is improved, but the circuit complexity and design difficulty increase
Solution Approach 1:
The logic circuit is designed to dynamically adapt its operation based on the active mode. During burn-in mode, it processes selection signals to generate control and selection signals for E-fuse programming. During normal mode, it compares address data with stored damaged cell addresses to identify matches. This dynamic reconfiguration allows a single circuit to maintain high identification accuracy across different operational phases without requiring multiple specialized circuits.
Solution Approach 2:
The logic circuit serves multiple purposes: generating control signals for E-fuse selection during burn-in mode, generating selection signals to activate specific E-fuse sections, and performing address comparison during normal mode. By consolidating these functions into a single multi-functional unit, the patent maintains precise damaged cell identification while significantly reducing circuit complexity compared to using separate dedicated circuits for each function.
Data Source
AI summary
An E-fuse circuit comprising: an E-fuse group, comprising a plurality of E-fuse sections, wherein each one of the E-fuse sections comprises a plurality of E-fuses; a multi-mode latch circuit, configured to receive an input signal to generate a first output signal in a burn in mode, and configured to receive an address to be compared to generate a second output signal in a normal mode; a first logic circuit group, configured to receive a first part of bits of the first output signal to generate a control signal in the burn in mode; and a second logic circuit group, configured to receive the control signal and a second part of bits of the first output signal to generate a selection signal in the burn in mode, to select which one of the E-fuse sections is activated.