Efuse Memory Redundancy for Programming Yield
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Solution Overview
Problem
Existing efuse memory technology faces low manufacturing yield due to programming failures, which require replacing entire rows or columns, and lacks efficient redundancy mechanisms to ensure accurate data storage and reading.
Innovation Solution
A memory device with an array of memory cells connected in series with redundant cells, using MOS transistors and sense amplifiers to program and read data, allowing for selective redundancy to compensate for programming failures without replacing entire rows or columns.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If efuse memory cells are programmed by melting the efuse with high current, then data can be stored in the memory cell, but programming failures occur reducing manufacturing yield
Solution Approach 1:
The patent applies beforehand cushioning by implementing redundant memory cells that are prepared in advance to compensate for potential programming failures. When a programming failure is detected in a primary memory cell, the corresponding redundant memory cell can be activated to provide the correct data, thereby cushioning against the impact of programming failures on manufacturing yield.
Solution Approach 2:
The patent changes the operational parameters by implementing a dual-mode reading mechanism that can switch between reading from primary memory cells and reading from redundant memory cells. This parameter change allows the system to adapt its behavior based on programming success, thereby improving reliability without permanently sacrificing productivity.
2Productivity
If redundant memory cells are added to compensate for programming failures, then manufacturing yield improves, but device complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the memory array into distinct primary memory cell regions and redundant memory cell regions. This segmentation allows the system to isolate and manage failures locally without affecting the entire memory device, thereby improving manufacturing yield while controlling complexity through structured organization.
Solution Approach 2:
The patent implements copying by creating redundant memory cells that are exact copies of the primary memory cells. These copies are used solely for error compensation purposes. The copying approach improves yield by providing backup data while maintaining relatively simple structure since the redundant cells are identical to the primary cells.
3Reliability
If entire rows or columns are replaced when programming failure occurs, then data accuracy is maintained, but device complexity and area increase
Solution Approach 1:
The patent applies local quality by implementing redundancy at the cell level rather than requiring replacement of entire rows or columns. Each primary memory cell has its corresponding redundant memory cell, allowing localized compensation for programming failures. This approach maintains data accuracy while significantly reducing device complexity compared to row or column-level redundancy.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution improves manufacturing yield by enabling accurate data storage and reading even after programming failures, reducing the need for replacing entire rows or columns and simplifying the memory device structure.
Implementation Method 1
when a high current flows through the efuse, the efuse may be melted and the resistance multiplies
Implementation Method 2
The ON/OFF state of the a column-select transistor is controlled by applying a gate voltage on the column-select transistor
Data Source
AI summary
The present disclosure provides a memory. The memory includes an array of memory cells arranged as a plurality of rows by a plurality of columns. A memory cell is connected to at least one redundant memory cell in series in a same row for storing same data as the memory cell; and a column of memory cells correspond to at least one redundant column of redundant memory cells wherein each redundant memory cell in the at least one redundant column stores same data as the memory cell in a same row.