E-fuse Circuit Ring Address Latch Serial Clock Encoding
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Solution Overview
Problem
Conventional memory testing requires multiple transmission lines for clock and address signals, leading to inefficiencies in the E-fuse circuit during testing stages, necessitating a novel E-fuse burning mechanism to reduce transmission lines and enable backup of input address data.
Innovation Solution
An E-fuse circuit incorporating a ring address latch that serially receives an input address and outputs a duplicated address at a different frequency, combined with a control signal generating circuit to decode and transmit control signals in parallel, allowing for E-fuse burning with reduced transmission lines and address backup through a ring latch circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate transmission lines are used for clock signal and address data, then signal transmission reliability is improved, but the number of transmission lines increases
Solution Approach 1:
The patent combines the clock signal and address data into a single transmission line by encoding the address data with the clock signal. The ring address latch uses the clock signal to control the serial transmission of address bits, allowing both timing and data to be conveyed through one line rather than requiring separate lines for clock and data
Solution Approach 2:
The single transmission line serves multiple functions: it transmits both the clock signal for timing control and the address data for selection. The ring address latch circuit enables this line to carry dual information streams by using the clock signal to gate the serial output of address bits, making the transmission line universal for both control and data purposes
2Device complexity
If address data is not backed up, then transmission line count is reduced, but testing reliability deteriorates
Solution Approach 1:
The ring address latch creates a backup copy of the address data by circulating it through the ring structure. The address bits are stored in the latch cells and can be re-transmitted if needed, providing a redundant copy of the address information without requiring additional transmission lines for backup
Data Source
AI summary
An E-fuse circuit comprising: a ring address latch, configured to receive a first input address arranged in serial i bits responding to a first clock signal, and to output a second input address arranged in serial j bits responding to a second clock signal; a control signal generating circuit, configured to receive the second input address, and to decode the second input address to generate first control signals with m bits and second control signals with n bits, wherein the first control signals and the second control signals are transmitted in parallel, and m, n are factors of j; and an E-fuse group, comprising j fuses. If any one of the first control signals has a first logic value and any one of the second control signals has the logic value, a corresponding fuse the E-fuse group is burned.