E-Fuse Array Area Reduction via Shared Select Transistor
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Solution Overview
Problem
Semiconductor e-fuse devices require a significant area due to the presence of multiple select transistors, which increases the stress on these transistors during operation, leading to potential damage and inefficiencies in programming and reading operations.
Innovation Solution
The design incorporates a single shared select transistor for multiple program transistors, reducing the overall area of the e-fuse array and minimizing stress on the select transistor by using a sharing doping region and metal lines to connect active regions, allowing for efficient programming and reading operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple select transistors are used for each program transistor, then the programming and reading operations can be performed independently, but the total area of the e-fuse array increases significantly
Solution Approach 1:
The patent merges multiple select transistor functions into a single shared select transistor that serves multiple program transistors. The select transistor is positioned to control access to multiple program transistors simultaneously, allowing independent programming and reading operations while occupying significantly less area than having separate select transistors for each program transistor.
Solution Approach 2:
The select transistor is designed with multi-functionality to handle both programming and reading operations for multiple program transistors. By making the select transistor universal rather than dedicated to a single program transistor, the patent achieves area reduction while maintaining operational independence through proper circuit design and control logic.
2Ease of operation
If multiple select transistors are arranged in parallel for each program transistor, then each program transistor can be controlled independently, but the stress on the select transistors increases leading to potential damage
Solution Approach 1:
The patent combines multiple select transistor functions into a single device, thereby reducing the total stress that would be distributed across multiple transistors. The shared select transistor is designed to handle the combined load through proper sizing and positioning, reducing the per-transistor stress while maintaining independent control capability through circuit architecture.
Solution Approach 2:
The shared select transistor acts as an intermediary that mediates access to multiple program transistors. By positioning the select transistor to control multiple program transistors through shared doping regions and metal lines, the patent distributes the control function while reducing the stress concentration that would occur with multiple dedicated select transistors.
3Area of stationary object
If a single shared select transistor is used for multiple program transistors, then the total area is reduced, but the complexity of connecting active regions increases
Solution Approach 1:
The patent resolves connection complexity by transitioning to a shared resource model where multiple program transistors share common doping regions and metal lines. This dimensional change in the connection architecture - from dedicated one-to-one connections to many-to-one sharing - reduces the number of required connections while maintaining area efficiency. The shared doping regions and metal lines create a simplified connection topology that manages complexity through resource sharing.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces the total area of the e-fuse array and alleviates stress on the select transistor, enhancing the reliability and efficiency of programming and reading operations while maintaining the functionality of the e-fuse.
Implementation Method 1
an operating voltage is applied to one of the first and second program gates, and the other one of the first and second program gates floats, so that one of the first dielectric layer and the second dielectric layer is selectively ruptured
Data Source
AI summary
An e-fuse including a substrate including a first active region and a second active region which are spaced from each other by an isolation region, a first program gate and a second program gate which are disposed over the first active region in parallel with each other, a single select gate disposed over the second active region; a sharing doping region formed in the first active region between the first program gate and the second program gate, a first doping region and a second doping region that are formed in the second active region on both sides of the select gate, a first metal line suitable for electrically coupling the sharing doping region to the first doping region and a second metal line connected to the second doping region.