E-Fuse Side Wall Fuse Links for Reduced Memory Cell Area
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Solution Overview
Problem
Conventional electrically programmable fuses (e-fuses) are limited by the minimum line width of the semiconductor process, resulting in large actual line widths and occupied area, which reduces memory storage capacity due to the requirement for high fusing currents and large transistor structures.
Innovation Solution
The e-fuse is designed with a semiconductor substrate having a preset active region and an isolating region with a height difference connected by side walls, allowing fuse links to be formed on these side walls, reducing the line width and fusing current requirements, and enabling smaller actual line widths and smaller transistor structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the e-fuse uses conventional planar structure with fuse links formed on the same plane as active regions, then the manufacturing process is simple, but the line width is limited by the minimum line width of the semiconductor process, resulting in large occupied area
Solution Approach 1:
The fuse links are formed on the side walls of trenches instead of on the same plane as the active regions. This vertical arrangement on side walls allows the fuse links to have a smaller effective width while maintaining electrical connectivity, thereby reducing the occupied area without compromising manufacturability through standard semiconductor processes.
2Area of stationary object
If the e-fuse line width is reduced below the limit line width of the semiconductor process, then the occupied area is reduced, but the fusing current requirement becomes difficult to meet with conventional structures
Solution Approach 1:
By forming fuse links on vertical side walls rather than horizontal planes, the effective cross-sectional area for current flow is reduced, allowing smaller line widths. The vertical geometry concentrates the current path, enabling the fuse to achieve fusing at lower current levels compared to conventional planar structures with equivalent or larger footprints.
Solution Approach 2:
The fuse links on the side walls have a localized concentrated current path with specific geometric characteristics that differ from planar fuse links. This local geometric quality optimization allows the fuse to require lower fusing current while occupying less area, as the current is concentrated through the vertical side wall structure rather than being distributed across a larger planar area.
3Power
If the transistor structure size is increased to provide sufficient fusing current, then the fusing requirement is met, but the area occupied by the memory cell increases
Solution Approach 1:
The trench-based side wall fuse link structure enables more efficient current utilization. The vertical geometry creates a concentrated current path that achieves fusing at lower current levels, allowing smaller transistor structures to provide sufficient fusing current without increasing the overall memory cell area.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design reduces the area occupied by a single memory cell, improving storage capacity while maintaining the reliability and programmability of e-fuses.
Implementation Method 1
based on the principle that electro-migration of fuse links contained in the e-fuse occurs under the drive of a certain magnitude of current, resulting in transition of the e-fuse from a low resistance state to a high resistance state
Data Source
Figure 1A~1B
Figure 1C~2
Figure 3A~3C
AI summary
An e-fuse and a manufacturing method thereof, and a memory cell are provided. The method includes: providing a semiconductor substrate, the semiconductor substrate including a preset active region; forming an isolating region on the semiconductor substrate, where the isolating region and the preset active region have a height difference and are connected by at least one side wall; forming a negative electrode and a positive electrode on the preset active region; and forming fuse links on the at least one side wall; for connecting the negative electrode and the positive electrode. Accordingly, the line width of the fuse links is out of the limitation of the limit line width of the semiconductor process, the actual line width of the e-fuse may be smaller than the limit line width of the semiconductor process, especially the limitation of the limit line width is eliminated under the same semiconductor process platform to realize small actual line width of the e-fuse, and low fusing current is required for fusing. Further, the transistor structure as a control unit is also small, thereby reducing the area occupied by a single memory cell, and improving the storage capacity of a memory.