EG-LDPC Decoder Architecture for High-Throughput Flash Memory

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Solution Overview

Problem

The existing decoder architectures for Euclidean Geometry Low Density Parity Check (EG-LDPC) codes face challenges in throughput and resource utilization, particularly in implementing high row and column weights, which hinders efficient error correction in advanced flash memory systems.

Innovation Solution

A decoder architecture is proposed with a check matrix comprising α*α sub-matrices, where check node updating and variable node updating circuits operate in sequential levels to calculate and update messages across layers and columns, utilizing shifting and delaying units to optimize message processing.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If existing decoder architectures for EG-LDPC codes are used, then implementation is simpler, but throughput is lower and resource utilization is poor

Engineering Contradiction:

ImprovethroughputVSAvoiddecoder architecture complexity

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The decoder architecture is segmented into multiple levels (first level, second level, third level) with each level containing specialized updating units. The check node updating circuit is divided into first updating units, and the variable node updating circuit is divided into second updating units. This segmentation allows parallel processing across levels while maintaining manageable complexity within each unit.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent introduces a hierarchical dimension to the decoder architecture by organizing updating units across multiple levels (first level, second level, third level) rather than using a flat single-level structure. This dimensional organization enables simultaneous operation of multiple updating units at different levels, significantly improving throughput while keeping individual unit complexity low.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Reliability

If high row and column weights are implemented, then error correction capability improves, but resource utilization decreases

Engineering Contradiction:

Improveerror correction capabilityVSAvoidresource utilization

Core Design Contradiction:

ReliabilityVSQuantity of substance

Solution Approach 1:

Multiple updating units at different levels are merged into a unified hierarchical architecture where first updating units and second updating units work together. The check node updating circuit and variable node updating circuit are combined in a coordinated manner, allowing efficient resource sharing while maintaining high error correction capability through the collective operation of all updating units.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The updating units are designed with multi-functionality to handle different types of node updates (check nodes and variable nodes) across multiple levels. Each updating unit can process different message types and participate in different error correction operations, maximizing resource utilization while supporting high row and column weights for improved reliability.

Inventive Principle:

Principle #6Universality (Multi-functionality)

3Quantity of substance

If sequential level-based updating is used, then resource utilization improves, but processing time increases

Engineering Contradiction:

Improveresource utilizationVSAvoidprocessing time

Core Design Contradiction:

Quantity of substanceVSLoss of time

Solution Approach 1:

The decoder employs periodic action by organizing updating units into discrete levels that operate in a structured sequence. First level updating units operate, then second level updating units operate, then third level updating units operate, creating a periodic pattern of updates. This periodic structure improves resource utilization by systematically activating different units while maintaining efficient processing through the repetitive nature of the update cycles.

Inventive Principle:

Principle #19Periodic action

Solution Approach 2:

The architecture performs preliminary actions by having first level updating units prepare and process messages before passing them to second level updating units, which in turn prepare messages for third level updating units. This preliminary processing at each level reduces the computational burden on subsequent levels, optimizing both resource utilization and processing efficiency through staged preparation and refinement of error correction messages.

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentUS12191882B1Decoders, decoding methods, memory controllers and memory systems

Publication Date: 2025.01.07 YANGTZE MEMORY TECH CO LTD

AI summary

The present disclosure provides a decoder including: a check node updating circuit and a variable node updating circuit. In a first time period, these circuits obtain the check node messages corresponding to different layers of the check matrix in the first updating units of different levels in the first updating units of α levels and obtain corresponding intermediate calculation values in the second updating units of different levels in the second updating units of α levels. After, the second updating units sequentially receive the check node messages corresponding to each layer of the check matrix and calculate the received check node messages with the intermediate calculation values of the second updating unit of the next level. From this, they obtain the variable node messages corresponding to different columns of the check matrix in the second updating units of different levels in the second updating units of α levels.