eGPIO Boundary Scan Cell for Multi-Voltage I/O Reuse
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Solution Overview
Problem
Conventional I/O architectures for semiconductor chips face challenges with increased silicon area overhead and yield risks due to high voltage circuitry requirements, as well as limited flexibility in repurposing dedicated I/O pads in applications where always-on subsystems are not used.
Innovation Solution
The implementation of an extended General Purpose I/O (eGPIO) boundary scan cell architecture that reduces high voltage routing by sharing level shifters and infrastructure across input, output, and test logic paths, allowing for multi-voltage I/O muxing without substantial high voltage circuitry, and enabling the reuse of I/Os dedicated to always-on subsystems for collapsible signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dedicated I/O pads are used for always-on subsystems, then reliability is improved, but adaptability deteriorates
Solution Approach 1:
The patent implements extended GPIO functionality that allows I/O pads to serve multiple purposes: they can be dedicated to always-on subsystems when needed, or repurposed for collapsible power domain signals when the always-on subsystem is not used. This multi-functional capability resolves the contradiction by enabling the same physical infrastructure to adapt to different operational requirements.
Solution Approach 2:
The patent introduces dynamic multiplexing capabilities that allow I/O pads to switch between different functional modes based on system state. The multiplexers and control logic enable runtime reconfiguration, allowing pads to transition from dedicated always-on subsystem interfaces to collapsible domain interfaces, thus providing both reliability for critical functions and adaptability for flexible resource allocation.
2Adaptability or versatility
If high voltage circuitry is implemented for I/O pads, then functionality is improved, but device complexity increases
Solution Approach 1:
The patent merges the high voltage circuitry requirements into a shared infrastructure that serves multiple I/O pads and multiple power domains. By consolidating level shifters and high voltage routing into common resources that can be dynamically allocated, the patent reduces overall device complexity while maintaining full functionality across all pads.
Solution Approach 2:
The patent introduces multiplexers and control logic as intermediary elements that manage the interface between different voltage domains. These intermediaries abstract the complexity of high voltage circuitry management, allowing the system to support multiple voltage domains and always-on subsystems without requiring each pad to have dedicated complex high voltage circuitry.
3Reliability
If separate I/O paths are provided for always-on and collapsible power domains, then reliability is improved, but area overhead increases
Solution Approach 1:
The patent combines the I/O paths for always-on and collapsible power domains into shared physical infrastructure. Multiplexers allow the same physical pads, level shifters, and routing to be dynamically allocated to different power domains based on operational mode, thereby reducing silicon area overhead while maintaining the reliability benefits of separate logical paths.
Solution Approach 2:
The patent creates universal I/O infrastructure that can serve multiple power domains and multiple functional modes. The shared level shifters, multiplexers, and routing structures can be dynamically configured to handle signals from always-on subsystems, collapsible power domains, or test logic, eliminating the need for dedicated separate paths and reducing overall area overhead.
Data Source
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AI summary
An extended General Purpose Input/Output (eGPIO) scheme is disclosed. In some implementations, an input/output (I/O) boundary scan cell comprises an output path to route output signals from a first voltage domain and signals from a second voltage domain to an I/O pad operating in a pad voltage domain, the output path having a first level shifter to up shift the output signals from the first voltage domain or the second voltage domain to the pad voltage domain; an input path to receive input signals from the I/O pad, the input path having a second level shifter to down shift the input signals from the pad voltage domain to the second voltage domain; and test logic to test signals in the first voltage domain and the second voltage domain.