eGPIO Boundary Scan Cell for Shared Level Shifting Across I/O Domains
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Solution Overview
Problem
Conventional I/O architectures in semiconductor chips face challenges with increased number of I/O pads, limited flexibility in repurposing dedicated I/Os, and high yield risk due to extensive high voltage circuitry required for multi-voltage I/O muxing.
Innovation Solution
The implementation of an extended General Purpose I/O (eGPIO) boundary scan cell that reduces high voltage routing by sharing level shifters and infrastructure across input, output, and control paths, allowing for multi-voltage I/O muxing without substantial high voltage circuitry, and enabling the reuse of I/Os dedicated to always-on subsystems for collapsible I/O signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional I/O architecture with dedicated I/Os for always-on subsystems is used, then reliability of always-on functionality is improved, but adaptability of I/O usage deteriorates
Solution Approach 1:
The eGPIO boundary scan cell enables I/O pads to serve multiple functions: they can be dedicated to always-on subsystems when needed, or repurposed for collapsible I/O signals during low power modes. The shared infrastructure and level shifters allow the same physical I/O pad to interface with different voltage domains dynamically, achieving multi-functionality that resolves the contradiction between reliability and adaptability.
Solution Approach 2:
The invention introduces dynamic reconfiguration capability where I/O pads can switch between being dedicated to always-on subsystems and being used for collapsible signals. The boundary scan cell dynamically adjusts its operation based on power mode, enabling the system to optimize I/O allocation in real-time, thus achieving both reliability for always-on functions and adaptability for power-saving modes.
2Adaptability or versatility
If extensive high voltage circuitry is added to support multi-voltage I/O muxing, then adaptability of I/O architecture is improved, but device complexity increases
Solution Approach 1:
The invention merges the boundary scan functionality with the I/O muxing infrastructure. The eGPIO boundary scan cell combines level shifters, input/output paths, and control logic into a single integrated unit that serves both testing and signal routing functions. This consolidation reduces the need for separate high voltage circuitry while maintaining adaptability for multi-voltage I/O operations.
Solution Approach 2:
The boundary scan cell is designed as a universal interface that handles multiple voltage domains through shared level shifters and control logic. Rather than implementing separate dedicated circuitry for each voltage domain, the universal boundary scan cell can dynamically interface with different voltage domains, reducing overall device complexity while maintaining adaptability.
3Reliability
If multiple dedicated I/O pads are provided for always-on subsystems, then reliability of signal routing is improved, but silicon area overhead increases
Solution Approach 1:
The invention makes I/O pads universal by enabling them to serve both always-on subsystems and collapsible I/O signals. Instead of allocating separate dedicated pads for always-on functions, the same pads can be dynamically assigned based on power mode, significantly reducing the total number of pads required while maintaining reliable signal routing for always-on functionality.
Solution Approach 2:
The system dynamically reconfigures I/O pad assignments based on power mode. During full power mode, pads can be dedicated to specific functions, while during low power modes, pads are dynamically repurposed for collapsible signals. This dynamic allocation ensures reliable routing for always-on functions while minimizing silicon area overhead by eliminating the need for permanently dedicated pads.
4Productivity
If I/O pads are repurposed during low power mode, then productivity of I/O resources is improved, but manufacturing precision requirements increase
Solution Approach 1:
The eGPIO boundary scan cell acts as an intermediary between the I/O pad and the core logic, providing a controlled interface that handles voltage domain transitions. This intermediary layer includes level shifters and control logic that manage the repurposing process, ensuring that voltage level transitions during low power mode are handled with precise control, thereby meeting manufacturing precision requirements while improving I/O resource productivity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution reduces silicon area overhead, minimizes high voltage wire routing, and extends multiplexing capabilities, enabling efficient signal processing and testing across multiple power domains while maintaining flexibility in I/O usage.
Implementation Method 1
the output path having a first level shifter to up shift the output signals from the first voltage domain or the second voltage domain to the pad voltage domain
Implementation Method 2
the input path having a second level shifter to down shift the input signals from the pad voltage domain to the second voltage domain
Data Source
AI summary
An extended General Purpose Input/Output (eGPIO) scheme is disclosed. In some implementations, an input/output (I/O) boundary scan cell comprises an output path to route output signals from a first voltage domain and signals from a second voltage domain to an I/O pad operating in a pad voltage domain, the output path having a first level shifter to up shift the output signals from the first voltage domain or the second voltage domain to the pad voltage domain; an input path to receive input signals from the I/O pad, the input path having a second level shifter to down shift the input signals from the pad voltage domain to the second voltage domain; and test logic to test signals in the first voltage domain and the second voltage domain.