Monolithic EIC-PIC Chip Integration with Region-Specific SOI Thickness
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Solution Overview
Problem
The manufacturing processes of electronic integrated circuits (EICs) and photonic integrated circuits (PICs) are different, leading to separate fabrication on different chips, which results in increased losses in electrical signals and high-speed operations, and the combination of EICs and PICs needs improvement for better integration.
Innovation Solution
A semiconductor device is developed with EICs and PICs fabricated simultaneously on a single chip using a semiconductor-on-insulator (SOI) substrate, where the EIC structure has a greater thickness than the PIC structure, and an interconnect structure is formed to electrically connect both, reducing transmission losses and signal delays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If EICs and PICs are fabricated separately on different chips using co-packaging technology, then the manufacturing processes can be optimized for each circuit type independently, but the electrical transmission path becomes longer and transmission loss increases
Solution Approach 1:
The patent merges EIC and PIC fabrication onto a single chip substrate, integrating both electronic and photonic circuits in one device. This eliminates the need for separate chips and co-packaging, thereby shortening electrical transmission paths and reducing transmission loss while maintaining independent optimization of each circuit type through region-specific processing.
Solution Approach 2:
The patent segments the single chip into distinct EIC regions and PIC regions with different semiconductor layer thicknesses. The EIC region has a first thickness optimized for electronic circuits, while the PIC region has a second thickness optimized for photonic circuits, allowing independent process optimization for each circuit type despite being on the same chip.
2Productivity
If EICs and PICs are fabricated separately on different chips, then each chip can be optimized for its specific circuit type, but the fabrication time and cost increase
Solution Approach 1:
The patent combines EIC and PIC fabrication into a single manufacturing process on one chip, which reduces fabrication time and cost compared to producing separate chips. This integration maintains the ability to optimize each circuit type through region-specific layer thickness and processing parameters.
3Device complexity
If a single chip is used for both EICs and PICs with different thickness requirements, then integration is achieved, but the manufacturing precision requirements increase
Solution Approach 1:
The patent applies local quality by having different semiconductor layer thicknesses in different regions of the same chip. The EIC region has a first thickness optimized for electronic circuits, while the PIC region has a second thickness optimized for photonic circuits. This allows each region to have the precise thickness it needs while being manufactured as a single integrated device.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach shortens electrical transmission paths, reduces fabrication costs and time, and facilitates miniaturization while enhancing the performance of both EICs and PICs by integrating them on a single chip.
Implementation Method 1
A thermal oxidation process is performed on the semiconductor layer in the PIC region to form an oxide layer
Data Source
AI summary
A method of fabricating a semiconductor device includes providing a substrate that includes a handle substrate, a bottom cladding layer, and a semiconductor layer stacked in sequence from bottom to top. The substrate includes an electronic integrated circuit (EIC) region and a photonic integrated circuit (PIC) region. A thermal oxidation process is performed on the semiconductor layer in the PIC region to form an oxide layer. A first thickness of the semiconductor layer in the EIC region is greater than a second thickness of the semiconductor layer below the oxide layer. The oxide layer is removed and a PIC structure is formed on the bottom cladding layer in the PIC region. An EIC structure is formed on the bottom cladding layer in the EIC region. An interconnect structure is formed to be electrically connected to the PIC and EIC structures.