Hybrid eIRA Decoder Scheduling for NAND Flash Parity Bits
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Solution Overview
Problem
NAND-type flash memory systems face challenges in iterative decoding due to vulnerability of parity bits using degree-2 and degree-1 variable nodes, which converge slowly and are prone to errors during decoding of extended irregular repeat-accumulate (eIRA) codes.
Innovation Solution
A memory controller and decoder architecture that performs separate update operations for user bits and parity bits, using a scheduler to control the order of operations, including variable node updates, check node updates, and parity node updates, employing hybrid scheduling and joint decoding schemes to improve decoding efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If iterative message-passing methods (SPA or MS algorithm) are used for decoding eIRA codes, then error correction capability is achieved, but convergence is slow and errors persist due to vulnerability of parity bits using degree-2 and degree-1 variable nodes
Solution Approach 1:
The decoding process is segmented into two distinct phases: a first phase performing variable node updates and check node updates for all bits, and a second phase performing only variable node updates specifically for parity bits associated with degree-2 and degree-1 check nodes. This segmentation allows targeted refinement of problematic parity bits without repeating unnecessary operations, thereby reducing overall decoding time while maintaining error correction capability.
Solution Approach 2:
The first phase of decoding performs preliminary updates on all variable and check nodes before the second phase focuses specifically on refining parity bit estimates. This preliminary action establishes a baseline decoding state, allowing the second phase to concentrate computational resources on the most vulnerable bits (degree-2 and degree-1 parity bits), thus improving convergence speed without sacrificing reliability.
2Measurement precision
If separate parity node update operation is performed for parity bits using results from variable node and check node updates, then decoding accuracy is improved, but operational complexity increases
Solution Approach 1:
The decoder architecture is segmented into distinct operational phases and components: a first decoder component handling variable and check node updates, and a second decoder component handling parity node updates. This segmentation improves decoding accuracy by dedicating specific resources to refining parity bit estimates, while the modular structure manages complexity through clear separation of functions.
Solution Approach 2:
The parity node update operation acts as an intermediary step that takes results from variable node and check node updates and refines parity bit estimates. This intermediary process improves decoding accuracy by specifically addressing the vulnerability of degree-2 and degree-1 parity bits, while the scheduler mediates the overall process to manage operational complexity through structured control.
3Productivity
If hybrid scheduling and joint decoding schemes are employed, then decoding efficiency is improved, but system complexity increases
Solution Approach 1:
The scheduler implements dynamic control by adapting the decoding process to the specific characteristics of eIRA codes, particularly the vulnerability of degree-2 and degree-1 parity bits. The system dynamically adjusts the decoding schedule to perform targeted updates in the second phase, improving decoding efficiency without requiring a complete redesign of the overall system architecture.
Solution Approach 2:
The decoder is divided into distinct components with specific responsibilities: variable node update operations, check node update operations, and parity node update operations. This segmentation improves decoding efficiency by allowing each component to be optimized for its specific function, while the scheduler coordinates these components to manage overall system complexity.
Data Source
AI summary
Memory controllers, decoders and methods to perform decoding of user bits and parity bits including those corresponding to low degree variable nodes. For each of the user bits, the decoder performs a variable node update operation and a check node update operation for connected check nodes. After all of the user bits are processed, the decoder performs a parity node update operation for the parity bits using results of the variable node and check node update operations performed on the user bits.