Electrical Impedance Tomography Chip Using Frequency Division Multiplexing
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Solution Overview
Problem
Existing electrical impedance tomography systems face challenges in reducing chip area and power consumption, limiting their integration of multiple channels and monitoring duration, especially for portable or wearable devices.
Innovation Solution
The implementation of frequency division multiplexing technology in the data compression block of the electrical impedance tomography chip, which modulates narrow-bandwidth signals from different channels into different frequencies and combines them into a wide-bandwidth signal, allowing for reduced hardware overhead and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If time division multiplexing is used to lower area consumption, then chip area is reduced, but switching time between channels limits monitoring duration and causes additional power consumption
Solution Approach 1:
The patent implements frequency division multiplexing where each channel is assigned a specific frequency for periodic signal injection and measurement. This allows simultaneous multi-channel operation without the switching delays inherent in time division multiplexing, thereby extending monitoring duration while maintaining compact chip area through integrated frequency synthesis circuits.
2Area of stationary object
If time division multiplexing is used, then area consumption is reduced, but additional power consumption is caused by the time division multiplexer
Solution Approach 1:
The system uses periodic frequency-division multiplexed signal injection where each channel operates on its assigned frequency simultaneously. This eliminates the need for power-hungry time-division multiplexers while maintaining area efficiency through integrated frequency synthesis and parallel signal processing paths.
3Measurement precision
If active electrode system is used to eliminate transmission distortion, then signal accuracy is improved, but redundant design increases area consumption and total cost
Solution Approach 1:
The patent implements a unified electrode control block that simultaneously performs current injection and voltage measurement functions for all electrodes. This multi-functional design eliminates the need for separate active electrode circuits while maintaining signal accuracy through frequency-division multiplexed measurement that rejects cable transmission distortion.
4Adaptability or versatility
If multiple channels are integrated, then monitoring capability is improved, but chip area and power consumption increase
Solution Approach 1:
The system uses frequency-division multiplexing where N channels share a single data acquisition circuit by assigning each channel a unique frequency. This allows N-channel monitoring capability while using only one set of ADC and processing circuits, reducing chip area by a factor of N compared to dedicated per-channel circuits.
Solution Approach 2:
The patent combines multiple channel signals into a single wideband signal that is processed by a unified data acquisition system. This merging approach consolidates multiple ADCs, buffers, and processing circuits into a single shared resource, dramatically reducing chip area and power consumption while maintaining full multi-channel functionality.
Data Source
AI summary
An electrical impedance tomography system with frequency division multiplexing based data compression comprising electrodes, a connecting line, an electrical impedance tomography chip, a universal serial bus and a computer. The present invention realizes the proposed electrical impedance tomography system by innovative application of frequency division multiplexing technology, and has the advantages of low power consumption and improved hardware overheads. The architecture of the 13-channel electrical impedance tomography chip introduced in the embodiment of the present invention, which applies the frequency division multiplexing based data compression technology, has taped out using CMOS 0.13 micrometer process; the power consumption per channel turns out to be 118 microwatts and the area is 0.87 square millimeters, verifying the effectiveness of the present invention. The present invention can also be migrated to other applications of electrical impedance tomography.