EL Display Gate Line Segmentation and Layering
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Solution Overview
Problem
Conventional thin film semiconductor devices for display apparatus face challenges in reducing line resistance of the gate line while maintaining suitable heat conductivity for semiconductor layer crystallization, leading to increased resistivity and potential disconnection issues due to bad connections between integrated and separate portions of the gate line, as well as increased parasitic capacitance and reduced aperture ratio.
Innovation Solution
The EL display panel design features a gate electrode and gate line formed in different layers, allowing for the selection of materials suitable for each component, with the gate line formed above the interlayer insulating film to reduce parasitic capacitance and IR drop, and an auxiliary line formed in the same layer as the gate line to increase aperture ratio and reduce unevenness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the gate line and gate electrode are formed in the same layer using material with small heat conductivity for suppressing heat radiation during laser annealing, then the crystallization of semiconductor layer is improved, but the line resistance of the gate line increases
Solution Approach 1:
The gate line is divided into two separate portions: an integrated portion formed in the same layer as the gate electrode using material with small heat conductivity (for good crystallization), and a separate portion formed in a different layer using material with small resistivity (for low line resistance). This segmentation allows each portion to optimize for its specific function.
Solution Approach 2:
The separate portion of the gate line is formed in a different layer (above the interlayer insulating film) rather than in the same layer as the gate electrode. This dimensional separation allows the use of different materials optimized for different functions without interfering with each other.
2Ease of manufacture
If the gate line is formed in the same layer as the gate electrode, then the manufacturing process is simplified, but parasitic capacitance between gate line and power supply line increases
Solution Approach 1:
The gate line is moved from the same layer as the gate electrode to a different layer (above the interlayer insulating film). This dimensional relocation increases the distance between the gate line and power supply lines, thereby reducing parasitic capacitance while still allowing for integrated formation in certain regions.
3Reliability
If auxiliary lines are formed in the EL unit layer, then electrical connection is achieved, but aperture ratio is reduced
Solution Approach 1:
The auxiliary line is relocated from the EL unit layer to a different layer (the same layer as the gate line, above the interlayer insulating film). This dimensional relocation maintains electrical connection functionality while removing the auxiliary line from the light-emitting area, thereby increasing the aperture ratio.
4Ease of manufacture
If the gate line is formed below the interlayer insulating film, then manufacturing is simplified, but disconnection issues occur due to bad connections between integrated and separate portions
Solution Approach 1:
The gate line is segmented into an integrated portion (below interlayer insulating film, formed with gate electrode) and a separate portion (above interlayer insulating film, formed separately). This segmentation allows the critical connection region to be isolated and properly formed, reducing disconnection issues.
Solution Approach 2:
The separate portion of the gate line is formed above the interlayer insulating film in a different layer, creating a more reliable connection structure that avoids the connection problems associated with forming the entire gate line below the insulating film.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively reduces line resistance, minimizes disconnection issues, decreases parasitic capacitance, and enhances the aperture ratio, resulting in improved display performance and longevity.
Implementation Method 1
a gate insulating film formed above the substrate to cover the gate electrode; a first interlayer insulating film formed above the gate insulating film to cover the first electrode and the second electrode
Implementation Method 2
the gate electrode and the gate line are electrically connected via a first conductive portion passing through the gate insulating film and the first interlayer insulating film
Data Source
AI summary
An EL display panel includes an organic EL device and a thin film semiconductor unit. The organic EL device includes a lower electrode, an organic light-emitting layer, and an upper electrode. The thin film semiconductor unit includes a first gate electrode, a gate insulating film, a first source electrode, a second drain electrode formed in a same layer as the first source electrode, a first power supply line formed in a same layer as the second drain electrode, and a first interlayer insulating film formed on the first source electrode and the second drain electrode. A gate line connected to the first gate electrode, a second power supply line formed in a same layer as the gate line and connected to the first power supply line, and an auxiliary line formed in a same layer as the second power supply line and connected to the upper electrode are included.