Elastic ADC Buffer GCD Control for Radar Chirp Variability
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Solution Overview
Problem
Conventional radar systems face design complexities due to variable ADC sampling rates and differing numbers of ADC samples within a frame, which existing solutions struggle to accommodate, particularly with high-speed interfaces that do not support changing clock rates or random burst sizes.
Innovation Solution
An elastic ADC buffer with a ping-pong mechanism, where a Greatest Common Divisor (GCD) is dynamically determined for each frame to standardize sample sizes across all chirps, allowing for flexible and efficient data transfer without requiring additional PLL-based clocks or increased HSI lane rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If variable ADC sampling rates and different numbers of ADC samples are used within a frame, then radar system performance is enhanced, but device complexity and design difficulty increase
Solution Approach 1:
The patent introduces an elastic buffer as an intermediary component between the ADC and HSI that absorbs the variability in sampling rates and sample counts. This buffer mediates the interface by storing variable-length chirp data and presenting it as uniform bursts to the HSI, thereby enabling performance enhancement without proportionally increasing design complexity.
Solution Approach 2:
The patent dynamically changes buffer parameters (buffer size, sample count) based on the actual ADC sampling rate and chirp requirements. By adjusting these parameters frame-by-frame or chirp-by-chirp, the system adapts to variable sampling conditions while maintaining a consistent interface protocol, thus improving versatility without permanent complexity increase.
2Adaptability or versatility
If additional PLL-based clocks or front-end filtering are added to support variable sampling rates, then sampling flexibility is improved, but device complexity and cost increase
Solution Approach 1:
The patent extracts the sampling rate conversion function from the traditional PLL-based clocking system and relocates it to the elastic buffer's control logic. By taking out the complex clock generation hardware and replacing it with a software-controlled buffer, the system achieves sampling flexibility while reducing component complexity and cost.
Solution Approach 2:
The patent replaces the mechanical/electrical clocking system (PLLs, phase shifters) with a software-controlled memory buffer system. The elastic buffer uses programmable logic and memory addressing to achieve sampling rate conversion, substituting complex analog clocking mechanisms with simpler digital control, thereby reducing component complexity.
3Productivity
If HSI lane data rate is increased to accommodate variable chirp sizes, then data transfer capability is improved, but device complexity and cost increase
Solution Approach 1:
The patent segments variable-length chirp data into fixed-size buffer blocks that are then transferred as uniform bursts over the HSI. By segmenting the data at the buffer level rather than requiring variable-rate HSI transfers, the system achieves high data transfer capability while maintaining a simple, fixed-rate HSI interface, thus avoiding increased interface complexity.
4Ease of operation
If ping-pong buffer is used to decouple ADC sampling rate from HSI data rate, then design flexibility is improved, but it fails when variable sample sizes are present
Solution Approach 1:
The patent transforms the static ping-pong buffer into a dynamic elastic buffer where the buffer size and operational parameters can change based on the actual chirp data characteristics. This dynamic adaptation allows the buffer to handle variable sample sizes while maintaining the decoupling benefit, thus achieving both design flexibility and variable chirp support simultaneously.
Data Source
AI summary
A method of radar signal processing includes providing an analog front end (AFE) including an amplifier coupled between an antenna and an ADC in a receive path, where an ADC output is coupled to an input of an elastic ADC buffer (elastic buffer) including a divided memory with for writing samples from the ADC (samples) while reading earlier written samples to a first signal processor by a high speed interface. A transmit path includes at least one power amplifier provided by the AFE coupled to drive an antenna. A Greatest Common Divisor (GCD) is determined across all chirps in a radar frame programmed to be used. For each frame a sample size for the elastic buffer is dynamically controlled constant to be equal to the GCD for reading samples from one memory block and writing samples to another memory block throughout all chirps in the frame.