Elastic Buffer Architecture for Non-Integer Clock Domain Ratios
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Solution Overview
Problem
Conventional elastic buffer designs struggle to accommodate non-synchronized clock domains with non-integer multiple clock speeds, leading to complexity and difficulty in achieving desired data rates.
Innovation Solution
An elastic buffer module with a memory unit of single-bit memory elements, using write and read index control modules to specify ranges for data input and output, and a central control unit for clock-skew-correction, allowing flexible word lengths and independent clock rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional elastic buffer designs are used, then data transfer between clock domains is achieved, but the design becomes complex and cannot accommodate non-integer multiple clock speeds
Solution Approach 1:
The buffer memory is segmented into multiple independently controllable banks (first buffer bank, second buffer bank, third buffer bank) with separate write and read ports. This segmentation allows different clock domains to access different segments simultaneously, enabling accommodation of non-integer multiple clock rate ratios while maintaining manageable complexity through modular design
Solution Approach 2:
The patent introduces a bank dimension to the traditional single-buffer architecture. By organizing memory into multiple banks that can be independently accessed, the system adds a spatial dimension to data access patterns, allowing parallel operations at different clock rates without increasing temporal complexity
2Adaptability or versatility
If additional buffers and gearboxes are used to accommodate different clock domains, then data transfer flexibility is improved, but chip area increases
Solution Approach 1:
Each buffer bank is designed with universal functionality to handle multiple clock domain interfaces. The banks can be configured to accept writes from different clock domains and provide reads to different clock domains, eliminating the need for dedicated buffers for each clock domain pair and reducing overall chip area
Solution Approach 2:
Multiple buffer banks are merged into a single elastic buffer module with unified control logic. The control unit manages all banks simultaneously, allowing the system to achieve the functionality of multiple separate buffers while sharing common control infrastructure and reducing redundant components
3Productivity
If conventional buffer designs are used, then data transfer is achieved, but latency is increased
Solution Approach 1:
The buffer banks are pre-configured with data in anticipatory fashion, allowing the control unit to prepare data for upcoming read operations. By maintaining multiple banks with different data sets, the system can switch between banks to minimize wait states and reduce latency without sacrificing transfer efficiency
Solution Approach 2:
While one buffer bank is being read from, another bank can simultaneously be written to, ensuring continuous useful action. This parallel operation eliminates idle time in the data transfer pipeline, maintaining high productivity while reducing overall latency through overlapping operations
Data Source
AI summary
An elastic buffer module includes: a memory unit configured as an array of memory elements; a write index control module that specifies a range of the memory elements into which a write word from a sequence of input words within input data is to be written into the memory unit; and a read index control module that specifies a range of the memory elements from which a read word is to be read from the memory unit and output as part of a sequence of read words in output data. The input words have a first bit width, the read words have a second bit width, the second bit width is a non-integer multiple of the first bit width, and the first bit width is a non-integer multiple of the second bit width.